Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
권호 표지

A Study on the TCAD Simulation to Predict the Latchup Immunity of High Energy Ion Implanted CMOS Twin Well Structures

고 에너지 이온 주입된 CMOS 쌍 우물 구조의 레치업 면역성 예측을 위한 TCAD 모의실험 연구

  • Published : 2000.02.01
Download PDF
⟨ Previous Next ⟩

Abstract

This study describes how a properly calibrated simulation method could be used to investigate the latchup immunity characteristics among the various high energy ion implanted CMOS twin well (retro-grade/BILLI/BL) structures. To obtain the accurate quantitative simulation analysis of retrograde well, a global tuning procedure and a set of grid specifications for simulation accuracy and computational efficiency are carried out. The latchup characteristics of BILLI and BL structures are well predicted by applying a calibrated simulation method for retrograde well. By exploring the potential contour, current flow lines, and electron/hole current densities at the holding condition, we have observed that the holding voltage of BL structure is more sensitive to the well design rule (p+to well edge space /n +to well edge space) than to the retrograde well itself.

Keywords

References

  1. Proc. IRPS Latchup characterization of high energy iion implanted new CMOS twin well that comprised the BILLI (Buried Implanted Layer for Lateral Isolation) and BL/CL (Buried Layer/Connecting Layer) structures J. K. Kim(et al.)
  2. IEEE Journal of Solid-State Circuits v.23 no.1 Parametric fomulation of CMOS latch-up as a function of chip layout parameters Ramesh Lohia;Akhtar Ali
  3. SEMICON/Korea 96 Buried layer/Connecting layer high energy implantation for improved CMOS latch-up W. Morris(et al.)
  4. IEMD tech. Digest Surface induced latch-up in VLSI CMOS circuits D. Takacs(et al.)
  5. IEEE Trans. Electron Devices v.41 no.5 Technological parameter and experimental set-up influence on latch-up triggering level in bulk CMOS devices J. P. Dubuc(et al.)
  6. IEEE Electron Device Letters v.12 no.2 The imipact of trench isolation in latch-up immunity in bulk nonepitaxial CMOS S. Bhattacharya(et al.)
  7. SISDAP v.7 TCAD Diagnosis of I/O-pin latchup in scaled-DRAM Katsumi Tsuneno(et al.)
  8. IEEE Trans. Electron Devices v.30 no.3 Disign model for bulk CMOS scaling enabling accurate latchup prediction Armin W. Wieder(et al.)
  9. TSUREM-4 ver. 6. 4, 2D process simulator Technology Modeling Associates, Inc.
  10. MEDICI ver. 4. 1, 2D device simulator Technology Modeling Associates, Inc.
  11. Latchup in CMOS Technology Ronald R. Troutman
  12. IEEE/IRPS Designing latchup robustness in a 0.35㎛ techology Ajith Amerasekera;S. Tamizh Selvam;Richard A. Chapman
  13. IEEE Trans. Electron Devices v.43 no.5 Two-dimensional simulation of local oxidation of silicon : Calibrated viscoelastic flow analysis Vincent Senez(et al.)
  14. Solid-State Electronics v.35 no.2 Unified apparent bandgap narrowing in n- and p- type silicon D. B. M. Klaassen;J. W. Slotboom;H. C. De Graaff