• Title/Summary/Keyword: junction structure

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Rheology of hydrophobic-alkali-soluble-emulsions (HASE) and the effects of surfactants

  • Lau, A.K.M.;Tiu, C.;Kealy, T.;Tam, K.C.
    • Korea-Australia Rheology Journal
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    • v.14 no.1
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    • pp.1-9
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    • 2002
  • Steady and dynamic shear properties of two hydrophobically modified alkali soluble emulsions (HASE), NPJI and NPJ2, were experimentally investigated. At the same polymer concentration, NPJ1 is appreciably more viscous and elastic than NPJ2. The high hydrophobicity of NPJ1 allows hydrophobic associations and more junction sites to be created, leading to the formation of a network structure. Under shear deformation, NPJ1 exhibits shear-thinning behaviour as compared with Newtonian characteristics of NPJ2. NPJ1 and NPJ2 exhibit a very high and a low level of elasticity respectively over the frequency range tested. For NPJ1, a crossover frequency appears, which is shifted to lower frequencies and hence, longer relaxation times, as concentration increases. Three different surfactants anionic SDS, cationic CTAB, and non-ionic TX-100 were employed to examine the effects of surfactants on the rheology of HASE. Due to the different ionic behaviour of the surfactant, each type of surfactant imposed different electrostatic interactions on the two HASE polymers. In general, at low surfactant concentration, a gradual increase in viscosity is observed until a maximum is reached, beyond which a continuous reduction of viscosity ensues. Viscosity development is a combined result of HASE-surfactant interactions, accompanied by constant rearrangement of the hydrophobic associative junctions, and electrostatic interactions.

The Short Channel Effect Immunity of Silicon Nanowire SONOS Flash Memory Using TCAD Simulation

  • Yang, Seung-Dong;Oh, Jae-Sub;Yun, Ho-Jin;Jeong, Kwang-Seok;Kim, Yu-Mi;Lee, Sang Youl;Lee, Hi-Deok;Lee, Ga-Won
    • Transactions on Electrical and Electronic Materials
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    • v.14 no.3
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    • pp.139-142
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    • 2013
  • Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

Prediction of Ultra-High ON/OFF Ratio Nanoelectromechanical Switching from Covalently Bound $C_{60}$ Chains

  • Kim, Han Seul;Kim, Yong-Hoon
    • Proceedings of the Korean Vacuum Society Conference
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    • 2013.02a
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    • pp.645-645
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    • 2013
  • Applying a first-principles computational approach combining density-functional theory and matrix Green's function calculations, we have studied the effects [2+2] cycloaddition olligormerization of fullerene $C_{60}$ chains on their junction charge transport properties. Analyzing first the microscopic mechanism of the switching realized in recent scanning tunneling microscope (STM) experiments, we found that, in agreement with experimental conclusions, the device characteristics are not significantly affected by the changes in electronic structure of $C_{60}$ chains. It is further predicted that the switching characteristics will sensitively depend on the STM tip metal species and the associated energy level bending direction in the $C_{60}-STM$ tip vacuum gap. Considering infinite $C_{60}$ chains, however, we confirm that unbound $C_{60}$ chains with strong orbital hybridizations and band formation should in principle induce a much higher conductance state. We demonstrate that a nanoelectromechanical approach in which the $C_{60}-STM$ tip distance is maintained at short distances can achieve a metal-independent and drastically improved switching performance based on the intrinsically better electronic connectivity in the bound $C_{60}$ chains.

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Current Progress in Fabrication of Ta and Nb based STJs for an Astronomical Detector

  • Yoon, Ho-Seop;Park, Young-Sik;Park, Jang-Hyun;Yang, Min-Kyu;Lee, Jeon-Kook;Chong, Yon-Uk;Lee, Yong-Ho;Lee, Sang-Kil;Kim, Dong-Lak;Kim, Sug-Whan
    • Bulletin of the Korean Space Science Society
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    • 2008.10a
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    • pp.37.3-37.3
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    • 2008
  • STJ(Superconducting Tunnel Junction) technique offers next generation photon detectors exhibiting high energy resolution, high quantum efficiency and photon counting ability over the broad wavelength range from X-ray to NIR. We report the succcess in fabrication of Ta/Al-AlOx-Al/Ta and Nb/Al-AlOx-Al/Nb micro structure deposited on sapphire substrates using various techniques including UV photolithography, DC Sputtering, RIE, and PECVD technique. The characterization experiment was undertaken in an Adiabatic Demagnetization Refrigerator at an operating temperature below 50mK. The details of experimental investigations for electrical characterization of STJ of $20\sim80{\mu}m$ in side-lengths are discussed. The measured I-V curves were used to derive The detector performance indicators such as energy gap, energy resolution, normal resistance, normal resistivity, dynamic resistance, dynamic resistivity, and quality factor.

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The Design of BCM based Power Factor Correction Control IC for LED Applications (LED 응용을 위한 BCM 방식의 Power Factor Correction Control IC 설계)

  • Kim, Ji-Man;Jung, Jin-Woo;Song, Han-Jung
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.6
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    • pp.2707-2712
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    • 2011
  • In this paper, a power factor correction (PFC) control circuit using single stage boundary conduction mode(BCM) for the 400V. 120W LED drive application has been designed. The proposed control circuit is aimed for improvement of the power factor correction and reduction of the total harmonic distortion. In this circuit, a new CMOS multiplier structure is used instead of a conventional BJT(bipolar junction transistor) based multiplier where has a relatively large area. The CMOS multiplier can bring 30 % reduced chip area, competitive die cost in comparison with the conventional BJT multiplier.

An Evaluation of the Structural Stability of a Clip Type Prefabricated Greenhouse under Strong Wind and Heavy Snow Conditions (조립식 클립형 비닐하우스의 강풍 및 폭설시 구조 안정성 평가)

  • Ro, Kyoung-Chul
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.15 no.6
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    • pp.3423-3428
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    • 2014
  • Numerical studies were performed to evaluate the structural safety of a greenhouse under both snow and wind loads. In the case of a wind load, fluid-structure interaction (FSI) method was used to consider the local pressure distributions on the greenhouse-induced by aerodynamic characteristics. The results showed that the maximum stress and deformation occur near the junction of pipe supports and rafters of the roof, where connecting clips are installed. Moreover, the wind load is a more severe condition than a snow load. Overall, these results will be used to design a prefabricated connecting clip with easy installation and low maintenance.

Design of a high speed and high intergrated ISL(Intergrated Schottky Logic) using a merged transistor (병합트랜지스터를 이용한 고속, 고집적 ISL의 설계)

  • 장창덕;이용재
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 1999.05a
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    • pp.415-419
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    • 1999
  • Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

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The Results Comparison of Measurement and Simulations in ISL(Integrated Schottky Logic) Gate (ISL 게이트에서 측정과 시뮬레이션의 결과 비교)

  • 이용재
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.5 no.1
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    • pp.157-165
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    • 2001
  • We analyzed the electrical characteristics of platinum silicide schottky junction to develope the voltage swing in Integrated Schottky Logic gates, and simulated the characteristics with the programs in this junctions. Simulation programs for analytic characteristics are the Medichi tool for device structure, Matlab for modeling and SUPREM V for fabrication process. The silicide junctions consist of PtSi and variable silicon substrate concentrations in ISL gates. Input parameters for simulation characteristics were the same conditions as process steps of the device farications process. The analitic electrical characteristics were the turn-on voltage, saturation current, ideality factor in forward bias, and has shown the results of breakdown voltage between actual characteristics and simulation characteristics in reverse bias. As a result, the forward turn-on voltage, reverse breakdown voltage, barrier height were decreased but saturation current and ideality factor were increased by substrates increased concentration variations.

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A Single-Flux-Quantum Shift Register based on High-T$_c$ Superconducting Step-edge Josephson Junctions

  • Sung, G.Y.;Choi, C.H.;Suh, J.D.;Han, S.K.;Kang, K.Y.;Hwang, J.S.;Yoon, S.G.;Jung, K.R.;Lee, Y.H.;Kang, J.H.;Kim, Y.H.;Hahn, T.S.
    • 한국초전도학회:학술대회논문집
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    • v.9
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    • pp.133-133
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    • 1999
  • We have fabricated and tested a simple circuit of the rapid single-flux-quantum(RSFQ) four-stage shift register using a single layer high-T$_c$ superconducting (HTS) YBa$_2Cu_3O_{7-x}$ (YBCO) thin film structure with 9 step-edge Josephson junctions. The circuit includes two read superconducting quantum interference devices(SQUID) and four stages. To establish a robust HTS RSFQ device fabrication process, we have focussed the reproducible process of sharp and straight step-edge formation as well as the ratio of film thickness to step height t/h. The spread of step-edge junction parameters was measured from each13 junctions with t/h=l/3, l/2, and 2/3 at various temperatures. We have demonstrated the simplified operation of the shift register at 65 K..

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A Study on the Channel Length and the Channel Punchthrough of Self-Aligned DMOS Transistor (자기정렬 DMOS 트랜지스터의 채널 길이와 채널 Punchthrough에 관한 고찰)

  • Kim, Jong-Oh;Kim, Jin-Hyoung;Choi, Jong-Su;Yoob, Han-Sub
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.11
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    • pp.1286-1293
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    • 1988
  • A general closed form expression for the channel length of the self-aligned double-diffused MOS transistor is obtained from the 2-dimensional Gaussian doping profile. The proposed model in this paper is composed of the doping concentration of the substrate, the final surface doping concentration and the vertical junction depth of the each double-diffused region. The calculated channel length is in good agreement with the experimental results. Also, the optimum channel structure for the prevention of the channel puncthrough is obtained by the averaged doping concentration in the channel region. A correspondence between the results of device simulation of channel punchthrough and the estimations of simplified model is confirmed.

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