• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.535-536
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• 2006

In the embedded system, external device interface that operates serial protocol with lower speed than the general computers is used commonly. This paper describes I2C bus protocol that is a bi-directional serial bus with a two-pin interface. The I2C bus requires a minimum amount of hardware to relay status and reliability information concerning the processor subsystem to an external device.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.507-511
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• 2018

This paper proposes a method for system development for high speed (300MHz) test of system IC semiconductors. The high-speed test system proposes a high-speed test circuit interface and a PCB design method for noise reduction. This paper proposes evaluation items and procedures for verifying the performance of the developed system. System IC The development of high speed test systems will help optimize the development of domestic system IC test equipment.

• The Magazine of the IEIE
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• v.19 no.6
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• pp.55-60
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• 1992

본 논문은 ISDN U-interface 회로 중에서 digital 부분의 설계에 대하여 기술하였다. 이 회로는 MMS43 code와 echo cancellation 방식을 사용하여 구현되었다. 회로 구성상 interface부분과 DSP부분으로 나누어 설계하였으며 gate-array ASIC을 이용하여 chip을 제작하였다. 공정은 1um CMOS 기술을 사용하였다.

• Journal of Sensor Science and Technology
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• v.3 no.1
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• pp.54-60
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• 1994

In this paper, the multi-sensor signal processing IC is designed. It consists of an analog multiplexer for selection of multi-sensor signals, active filters for noise rejection and signal amplification, and a sample and hold circuit for interface with digital signal processing. By implementing these circuits with CMOS transistors, integration, low power dissipation and miniaturization of the total signal processing system have been made possible.

• Journal of the Korean institute of surface engineering
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• v.32 no.6
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• pp.647-657
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• 1999

Due to the inherently poor adhesion strength of Cu-based leadframe/EMC (Epoxy Molding Compound) interface, popcorn cracking of thin plastic packages frequently occurs during the solder reflow process. In the present work, in order to enhance the adhesion strength of Cu-based leadframe/EMC interface, black-oxide layer was formed on the leadframe surface by chemical oxidation of leadframe, and then oxidized leadframe sheets were molded with EMC and machined to form SDCB (Sandwiched Double-Cantilever Beam) and SBN (Sandwiched Brazil-Nut) specimens. SDCB and SBN specimens were designed to measure the adhesion strength between leadframe and EMC in terms of critical energy-release rate under quasi-Mode I ($G_{IC}$ ) and mixed Mode loading ($G_{C}$ /) conditions, respectively. Results showed that black-oxide treatment of Cu-based leadframe initially introduced pebble-like X$C_2$O crystals with smooth facets on its surface, and after the full growth of $Cu_2$O layer, acicular CuO crystals were formed atop of the $Cu_2$O layer. According to the result of SDCB test, $Cu_2$O crystals on the leadframe surface did not increase ($G_{IC}$), however, acicular CuO crystals on the $Cu_2$O layer enhanced $G_{IC}$ considerably. The main reason for the adhesion improvement seems to be associated with the adhesion of CuO to EMC by mechanical interlocking mechanism. On the other hand, as the Mode II component increased, $G_{C}$ was increased, and when the phase angle was -34$^{\circ}$, crack Kinking into EMC was occured.d.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.10
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• pp.2282-2291
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• 1997

This paper describes an IC design for the HCR protocol which is designed to accomodata both real and non-real time data for high-speed multimedia services. The designed HCR IC is perfectly compatible with the conventional ATM IC's and physical layer IC's. The standard UTOPIA interface is adopted. Simulation results show that the proposed HCR IC operates very well according to the priority and the quota state of the real and non-real time data. The proposed HCR IC can be merged into the conventional ATM IC's without any modification and will be useful for multimedia service applications.

• Proceedings of the Korea Contents Association Conference
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• 2004.11a
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• pp.412-416
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• 2004

In this paper, we designed data transformation interface for automation of PCB product. For this, information of PCB components designed to CAD is analyzed and human error detect algorithm is developed. Also we constructed information of IC components in database and designed the interface and algorithm for data transformation. Thersfore Did so that can shorten time of degree to be 1-2 days within several minutes by automating existent manual processing.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.6
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• pp.709-716
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• 2004

In order to prevent the interface delamination of an plastic IC package in the infrared (IR) soldering process, we tried to reduce stress by parameterization, sensitivity analysis and unconstraint optimization. The design variables of dimensions and material properties are determined among all the possible variables from the parametric study. Their optimized values are determined by applying the unconstraint optimization to the parameterized IC package. The maximum von-Mises stress value decreases greatly by optimum design.

• Transactions of the Korean Society of Automotive Engineers
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• v.16 no.3
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• pp.15-22
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• 2008

Applications of bonded dissimilar materials such as integrated circuit(IC) packages, ceramics/metal and resin/metal bonded joints, are very increasing in various industry fields. It is very important to analyze the thermal stress and stress singularity at interface edge in bonded joints of dissimilar materials. In order to investigate the IC package crack propagating from the edge of die pad and resin, the fracture parameters of bonded dissimilar materials and material properties are obtained. In this paper, the thermal stress and its singularity index for the IC package were analyzed using 2-dimensional elastic boundary element method(BEM). From these results, crack propagation direction and path by thermal stress in the IC package were numerically simulated with boundary element method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.12
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• pp.2503-2510
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• 2015

This paper presents a single-phase energy measurement IC to measure electric power quantities. The entire IC includes two programmable gain amplifiers (PGAs), two ${\sum}{\Delta}$ modulators, a reference circuit, a low-dropout (LDO) regulator, a temperature sensor, a filter unit, a computation engine, a calibration control unit, registers, and an external interface block. The proposed energy measurement IC is fabricated with $0.18-{\mu}m$ CMOS technology and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4,096 kHz and consumes 10 mW in 3.3 V supply.