• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제54권7호
• /
• pp.299-303
• /
• 2005

This paper proposes an analytic method can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

• 전자공학회논문지SC
• /
• 제39권2호
• /
• pp.146-156
• /
• 2002

이 논문에서는 불규칙한 배선 구조에 대한 가상직선(virtual-straight line) 파라미터 추출 방법과 이를 이용한 새롭고 빠른 시간 영역에서의 시뮬레이션 방법론을 보이고 검증한다. 비선형인 트랜지스터의 특성을 고려한 인터컨넥트 회로의 시간영역에서의 신호응답은 모델차수감소법(model order reduction method)을 사용하여 수행된다. 모델차수감소법은 인터컨넥트 회로의 단위길이당 파라미터를 이용하므로 인터컨넥트의 길이가 서로 다르고 불규칙한 형태를 갖는 인터컨넥트에 대해서 직접적으로 모델차수감소법을 적용하기 위해 가상직선 모델을 사용하여 인터컨넥트의 파라미터를 추출한다. 또한 모델차수감소법은 일반적인 Berkeley SPICE의 모듈로 구성하여 인터컨넥트 회로의 시간영역 시간응답을 구하였으며 일반적인 회로 시뮬레이터인 HSPICE의 시뮬레이션 결과와 비교하여 잘 일치한다는 것을 보인다. 제안된 방법은 복잡한 다층 배선 구조에 대한 신속하고 정확한 시간영역 신호응답을 제공함으로써 고성능 VLSI 회로 설계에 유용하게 적용할 수 있다.

• 대한전자공학회논문지SD
• /
• 제46권9호
• /
• pp.25-32
• /
• 2009

최근 네트워크-온-칩(Network-on-chip)에 대한 연구가 활발히 진행되고 있는 가운데 반도체 칩 복잡도 증가와 고성능에 대한 요구로 인해 기존 구리 기반의 상호연결(Copper-based interconnects)을 사용할 경우 성능, 전력, 대역폭 등에 대한 설계 한계에 곧 직면할 것으로 보인다. 이 문제에 대한 대안으로 전기적인 상호연결(Electrical Interconnects, EIs)과 광학적 상호연결(Optical Interconnects, OIs)을 상호 보완적으로 사용하는 방법이 제안되고 있다. 이러한 연구 방향의 일환으로, 본 논문에서 광학적 상호연결은 지연 시간을 감안하여 임계 경로에, 전기적인 상호연결은 비 임계 경로에 적용하며, 두 상호연결을 혼용하여 사용하기 위한 효율적인 하이브리드 스위치 구조와 라우팅 최적화 방법을 제안한다. 모의실험 결과 제안한 알고리즘과 구조를 적용할 경우 전기적인 상호연결만을 사용 할 경우보다 최대 25%의 속도 향상과 38%의 소비 전력 감소를 나타냈다.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
• /
• pp.146-150
• /
• 2001

Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe. And the cascade transmission matrix conversion was performed. The same measurements and conversion techniques were conducted on the assembled test chip and substrate at the same frequency range. Then impedance values in ACF flip-chip interconnection were extracted from cascade transmission matrix. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of SiO$_2$filler to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. High frequency behavior of metal Au stud bumps was investigated. The resonance frequency of the metal stud bump interconnects is higher than that of ACF flip-chip interconnects and is not observed at the microwave frequency band. The extracted model parameters of adhesive flip chip interconnects were analyzed with the considerations of the characteristics of material and the design guideline of ACA flip chip for high frequency applications was provided.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.393-394
• /
• 2008

Carbon nanotubes are attractive nano-structured materials because of their remarkable electronic, physical, chemical properties. Due to these reasons, application researches of CNTs are actively processed on the display, the electronic element, the nano-diode fields and the semiconductor element. Today, The major issue of semiconductor technique are via and interconnects. CNTs are used to make via and interconnects because of high electric currents density and high heat transfer. Control of the orientation of grown CNTs is very important thing for making via and interconnects. Via are horizontal growth of CNTs and interconnects are vertical growth of CNTs. This research is based on the experiment using control of gas flow directions and DC bias. Scanning Electron Microscope (SEM) was used to check this experiment.

• 한국세라믹학회지
• /
• 제52권5호
• /
• pp.344-349
• /
• 2015

An interconnect is the key component of solid oxide fuel cells that electrically connects unit cells and separates fuel from oxidant in the adjoining cells. To improve their surface stability in high-temperature oxidizing environments, metallic interconnects are usually coated with conductive oxides. In this study, lanthanum nickelates ($LaNiO_3$) with a perovskite structure are synthesized and applied as protective coatings on a metallic interconnect (Crofer 22 APU). The partial substitution of Co, Cu, and Fe for Ni improves electrical conductivity as well as thermal expansion match with the Crofer interconnect. The protective perovskite layers are fabricated on the interconnects by a slurry coating process combined with optimized heat-treatment. The perovskite-coated interconnects show area-specific resistances as low as $16.5-37.5m{\Omega}{\cdot}cm^2$ at $800^{\circ}C$.

• 대한전자공학회논문지SD
• /
• 제46권10호
• /
• pp.70-78
• /
• 2009

본 논문에서는 고속 저전압 차동 신호(Low-Voltage Differential Signaling, LVDS) 전송방식의 응용을 위한 전송선 분석 및 설계 최적화 방법을 제안한다. 차동 전송 경로 및 저전압 스윙 방법의 발전으로 인해 저전압 차동 신호 전송방식은 데이터 통신 분야, 고 해상도 디스플레이 분야, 평판 디스플레이 분야에서 매우 적은 소비전력, 개선된 잡음 특성 및 고속 데이터 전송률을 제공한다. 본 논문은 차동 유연성 인쇄 회로 보드(flexible printed circuit board, FPCB) 전송선에서 선 폭, 선 두께 및 선간격과 같은 전송선 설계 변수들의 최적화 기법을 이용하여 직렬 접속된 전송선에서 발생하는 임피던스 부정합과 신호 왜곡을 감소시키기 위해 개선 모델과 개발된 수식을 제안한다. 이러한 차동 FPCB 전송선의 고주파 특성을 평가하기 위해 주파수 영역에서 전파(full-wave) 전자기 시뮬레이션 및 시간 영역 시뮬레이션을 각각 수행하였다. 본 논문에서 제안하는 방법은 저전압 차동 신호 방식의 응용을 위한 고속 차동 FPCB 전송선을 최적화하는데 매우 도움이 되리라 믿는다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
• /
• pp.573-576
• /
• 2004

This paper proposes an analytic method that can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제53권10호
• /
• pp.539-545
• /
• 2004

In this paper, we consider the problem of capacitance matrix calculation for strip-line and other interconnects crossings. The problem is formulated in the spectral domain using the method of moments. Sinc-functions are employed as basis functions. Conventionally, such a formulation leads to a large, non-sparse system of linear equations in which the calculation of each of the coefficient requires the evaluation of a Fourier-Bessel integral. Such calculations are computationally very intensive. In the method proposed here, we provide simplified expressions for the coefficients in the moment method matrix. Using these simplified expressions, the coefficients can be calculated very efficiently. This leads to a fast evaluation of the capacitance matrix of the structure. Computer simulations are provided illustrating the validity of the method proposed.

• Journal of Electrical Engineering and Technology
• /
• 제6권2호
• /
• pp.233-238
• /
• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.