• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.5
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• pp.44-53
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• 1999

This paper are reported a methodology and application for extracting parasitic capacitances in a multi-level interconnect semiconductor structure by a numerical technique. To calculate the parasitic capacitances between the interconnect lines, we employed finite element method (FEM) and calculated the distrubution of electric potential in the inter-metal layer dielecric(ILD) by solving the Laplace equation. The three-dimensional multi-level interconnect structure is generated directly from two-dimensional mask layout data by specifying process sequences and dimension. An exemplary structure comprising two metal lines with a dimension of 8.0$\times$8.0$\times$5.0$\mu\textrm{m}^3/TEX>, which is embedded in three dielectric layer, was simulated to extract the parasitic capacitances. In this calculation, 1960 nodes with 8892 tetrahedra were used in ULTRA SPARC 1 workstation. The total CPU time for the simulation was 28 seconds, while the memory size of 4.4MB was required.

• Korean Journal of Materials Research
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• v.2 no.3
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• pp.228-238
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• 1992

An investigation on the step-coverage of PECVD and $O_3$ ThCVD oxides was undertaken to implement into the void-free inter metal dielectric planarization using multi-chamber system for the submicron double level metallization. At various initial aspect ratios the instantaneous aspect ratios were measured through modelling and experiment by depositing the oxides up to $0.9{\mu}m$ in thickness in order to monitor the onset of void formation. The modelling was found to be in a good agreement with the observed instantaneous aspect ratio of TEOS-based PECVD oxide whose re-entrant angle was less than $5^{\circ}$. It is demonstrated that either keeping the instantaneous aspect ratio of PECVD oxide as a first layer less than a factor of 0.8 or employing Ar sputter etch to create sloped oxide edge ensures the void-free planarization after$O_3$ ThCVD oxide deposition whose step-coverage is superior to PECVD oxide. It has been observed that $O_3$ ThCVD oxide etchback scheme has shown higher yield of via contact chain than non etchback process, with resistance per via contact of $0.1~0.3{\Omega}/{\mu}m^2$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.434-435
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• 2012

Plasma enhanced chemical vapor deposition (PECVD) silicon dioxide thin films have many applications in semiconductor manufacturing such as inter-level dielectric and gate dielectric metal oxide semiconductor field effect transistors (MOSFETs). Fundamental chemical reaction for the formation of SiO2 includes SiH4 and O2, but mixture of SiH4 and N2O is preferable because of lower hydrogen concentration in the deposited film [1]. It is also known that binding energy of N-N is higher than that of N-O, so the particle generation by molecular reaction can be reduced by reducing reactive nitrogen during the deposition process. However, nitrous oxide (N2O) gives rise to nitric oxide (NO) on reaction with oxygen atoms, which in turn reacts with ozone. NO became a greenhouse gas which is naturally occurred regulating of stratospheric ozone. In fact, it takes global warming effect about 300 times higher than carbon dioxide (CO2). Industries regard that N2O is inevitable for their device fabrication; however, it is worthwhile to develop a marginable nitrous oxide free process for university lab classes considering educational and environmental purpose. In this paper, we developed environmental friendly and material cost efficient SiO2 deposition process by substituting N2O with O2 targeting university hands-on laboratory course. Experiment was performed by two level statistical design of experiment (DOE) with three process parameters including RF power, susceptor temperature, and oxygen gas flow. Responses of interests to optimize the process were deposition rate, film uniformity, surface roughness, and electrical dielectric property. We observed some power like particle formation on wafer in some experiment, and we postulate that the thermal and electrical energy to dissociate gas molecule was relatively lower than other runs. However, we were able to find a marginable process region with less than 3% uniformity requirement in our process optimization goal. Surface roughness measured by atomic force microscopy (AFM) presented some evidence of the agglomeration of silane related particles, and the result was still satisfactory for the purpose of this research. This newly developed SiO2 deposition process is currently under verification with repeated experimental run on 4 inches wafer, and it will be adopted to Semiconductor Material and Process course offered in the Department of Electronic Engineering at Myongji University from spring semester in 2012.

• Korean Journal of Materials Research
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• v.2 no.1
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• pp.76-82
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• 1992

Deposition of $TEOS-O_3$ oxide film as inter-metal dielectric layer shows the substrate dependency according to the substrate material and pattern density and pitch size. To minimize substrate and Pattern dependency, TEOS-base and $SiH_4-base$ Plasma oxide were predeposited as underlying material on the substrate. The substrate dependency of $TEOS-O_3$ oxide film was more significant on TEOS-base plasma oxide than on $SiH_4-base$ plasma oxide. The dependency of $TEOS-O_3$ oxide film was remarkably reduced, or nearly eliminated, by $N_2$plasma treatment on TEOS-base plasma oxide, which appears to be caused by the O-Si-N structure, observed on the the surface of TEOS-base plasma oxide.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.31-36
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• 2018

This research scrutinizes the reason of failure after pressure cooker test (PCT) for DRAM device. We use the physical inspecting tools, such as microscope, SEM and TEM, and finally find the discolor phenomenon, corrosion of Al and delamination of inter-metal dielectric (IMD) in the failed devices after PCT. Furthermore, we discover the abnormal $Al_XO_Y$ layer on Al through the careful additional measurements. To find the reason, we evaluate the effect of package ball size and pinhole in passivation layer. Unfortunately, those aren't related to the problems. We also estimate halide effect of Al. The halogens such like Cl are contained within EMC material. Those result in the slight improving of PCT characteristics but do not perfectly solve the problems. We make a hypothesis of Galvanic corrosion. We can find the residue of Ti at the edge of pad open area. We can see the improving the PCT characteristics by the time split of repair etch. The possible mechanism of the PCT failure can be deduced as such following sequence of reactions. The remained Ti reacts on the pad Al by Galvanic corrosion. The ionized Al is easily react with the $H_2O$ supplied under PCT environment, and finally transfers to the abnormal $Al_XO_Y$ layer.