• 한국소음진동공학회:학술대회논문집
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• 한국소음진동공학회 2008년도 추계학술대회논문집
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• pp.286-292
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• 2008

Transverse flux machine (TFM) has been developed to drive a machine of large input power at low-speed. However, it has complicated structure and large torque ripple due to its inherent structure In this paper the characteristics of torque of a rotatory two-phase TFM are analyzed by using the 3-dimensional finite to element method and optimal design. This research shows that one of the effective design variables is the skew angle of permanent magnet. The skew angles of permanent magnet are optimized by using a Progressive Quadratic Response Surface Method (PQRSM). It also shows that the proposed optimal skew magnet not only increases average torque but also decreases torque ripple of a rotatory two-phase TFM.

• 한국소음진동공학회논문집
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• 제19권10호
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• pp.1003-1011
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• 2009

Transverse flux machine(TFM) has been developed to drive a machine of large input power at low-speed. However, it has complicated structure and large torque ripple due to its inherent structure. In this paper the characteristics of torque of a rotatory two-phase TFM are analyzed by using the 3-dimensional finite element method and optimal design. This research shows that one of the effective design variables is the skew angle of permanent magnet. The skew angles of permanent magnet are optimized by using a genetic algorithm. It also shows that the proposed optimal skew magnet not only increases average torque but also decreases torque ripple of a rotatory two-phase TFM.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.246-248
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• 2007

This paper presents fast locking PLL(Phase Locked Loop) that can improve a jitter noise characteristics and acquisition process by designing a PFD(Phase Frequency Detector) circuit. The conventional PFD has not only a jitter noise caused from such a demerit of the wide dead zone and duty cycle, but also a long delay interval that makes a high speed operation unable. The advanced PFD circuit using the TSPC(True Single Phase Clocking) circuit is proposed, and it has excellent performances such as 1.75us of locking time and independent duty cycle characteristic. It is fabricated in a 0.018-${\mu}m$ CMOS process, and 1.8v supply voltage, and 25MHz of input oscillator frequency, and 800MHz of output frequency and is simulated by using ADE of Cadence.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 학술대회 논문집 전문대학교육위원
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• pp.154-158
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• 2006

The switching-mode power converter has been widely used because of its features of high efficiency and small weight and size. These features are brought by the ON-OFF operation of semiconductor switching devices. However, this switching operation causes the surge and EMI(Electromagnetic Interference) which deteriorate the reliability of the converter themselves and entire electronic systems. This problem on the surge and noise is one of the most serious difficulties in AC-to-DC converter. Random Pulse Width Modulation (RPWM) is peformed by adding a random perturbation to switching instant while output-voltage regulation of converter is performed. RPWM method for reducing conducted EMI in single switch three phase discontinuous conduction mode boost converter is presented. The more white noise is injected, the more conducted EMI is reduced. But output-voltage is not sufficiently regulated. This is the reason why carrier frequency selection topology is proposed. In the case of carrier frequency selection, output-voltage of steady state and transient state is fully regulated. A RPWM control method was proposed in order to smooth the switching noise spectrum and reduce it's level. Experimental results are verified by converter operating at 300v/1kW with $5%{\sim}30%$ white noise input. Spectrum analysis is performed on the Phase current and the CM noise voltage. The former is measured with Current Probe and the latter is achieved with LISN, which are connected to the spectrum analyzer respectively.

• ETRI Journal
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• 제33권3호
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• pp.366-373
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• 2011

In this paper, we propose a low-power all-digital phase-locked loop (ADPLL) with a wide input range and a high resolution time-to-digital converter (TDC). The resolution of the proposed TDC is improved by using a phase-interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 $mm^2$ using 0.13 ${\mu}m$ CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is -120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.

• 한국항해항만학회:학술대회논문집
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• 한국항해항만학회 2006년도 International Symposium on GPS/GNSS Vol.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• 한국산업정보학회논문지
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• 제6권4호
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• pp.48-53
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• 2001

TMT-2000 기지국용 3단 저잡음 증폭기를 설계하고 제작한다. 첫째 단에서의 증폭소자는 잡음특성이 좋은 GaAs HJ-FET를 사용하고, 둘째 및 셋째 단에는 이득과 출력전압이 높은 값을 갖도록 하기 위해 모노리딕(monolithic) 마이크로웨이브 집적회로를 사용한다. 또한 입력 정재파비를 낮추기 위해서 평형증폭기를 사용하는데, 이 평형증폭기의 위상차로 인한 잡음지수를 최소화하기 위해서 첫째 단에만 제한적으로 사용한다. 제작된 증폭기는 동작 주파수에서 이득 39.74$\pm$0.4dB, 최대잡음지수 0.97dB, 입.출력 정재파비 1.2 이하 및 OIP$_3$ 특성은 38.17dBm을 나타낸다.

• 전기학회논문지P
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• 제51권3호
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• pp.120-125
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• 2002

The switching-mode power converter has been widely used because of its features of high efficiency and small weight and size. These features are brought by the ON-OFF operation of semiconductor switching devices. However, this switching operation causes the surge and EMI(Electromagnetic Interference) which deteriorate the reliability of the converter themselves and entire electronic systems. This problem on the surge and noise is one of the most serious difficulties in AC-to-DC converter. In the switching-mode power converter, the output voltage is generally controlled by varying the duty ratio of main switch. When a converter operates in steady state, duty ratio of the converter is kept constant. So the power of switching noise is concentrated in specific frequencies. Generally, to reduce the EMI and improve the immunity of converter system, the switching frequency of converter needs to be properly modulated during a rectified line period instead of being kept constant. Random Pulse Width Modulation (RPWM) is performed by adding a random perturbation to switching instant while output-voltage regulation of converter is performed. RPWM method for reducing conducted EMI in single switch three phase discontinuous conduction mode boost converter is presented. The more white noise is injected, the more conducted EMI is reduced. But output-voltage is not sufficiently regulated. This is the reason why carrier frequency selection topology is proposed. In the case of carrier frequency selection, output-voltage of steady state and transient state is fully regulated. A RPWM control method was proposed in order to smooth the switching noise spectrum and reduce it's level. Experimental results are verified by converter operating at 300V/1kW with 5%~30% white noise input. Spectrum analysis is performed on the Phase current and the CM noise voltage. The former is measured with Current Probe and the latter is achieved with LISN, which are connected to the spectrum analyzer respectively.

• 한국전자파학회논문지
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• 제11권6호
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• pp.959-968
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• 2000

본 논문에서는 낮은 위상 잡음을 갖는 B-WLL대역 국부발진기(LO)로 사용될 주파수 합성기를 설계 및 제작하였다. 2GHz 대역의 주파수 합성기를 구성, 낮은 위상잡음의 안정된 파형을 얻은 후 SRD(Step Recovery Diode)를 이용하여 주파수 체배기를 거쳐 12GHz 대역의 위상 고정된 안정된 신호를 얻었다. 제작된 주파수 합성기는 각각 출력 주파수 24.92 GHz, 25.10GHz, 25.26GHz를 가지며, 이 중 출력 주파수 24.92 GHz에서 0.44 dB의 발전출력과 -87.93 dB/Hz(@10KHz), -109,54dBc/Hz(@100 KHz)의 위상잡음 특성을 나타내었다.

• ETRI Journal
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• 제42권6호
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• pp.943-950
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• 2020

We propose 8.2-GHz band radar RFICs for an 8 × 8 phased-array frequency-modulated continuous-wave receiver developed using 65-nm CMOS technology. This receiver panel is constructed using a multichip solution comprising fabricated 2 × 2 low-noise amplifier phase-shifter (LNA-PS) chips and a 4ch RX front-end chip. The LNA-PS chip has a novel phase-shifter circuit for low-voltage operation, novel active single-to-differential/differential-to-single circuits, and a current-mode combiner to utilize a small area. The LNA-PS chip shows a power gain range of 5 dB to 20 dB per channel with gain control and a single-channel NF of 6.4 dB at maximum gain. The measured result of the chip shows 6-bit phase states with a 0.35° RMS phase error. The input P1 dB of the chip is approximately -27.5 dBm at high gain and is enough to cover the highest input power from the TX-to-RX leakage in the radar system. The gain range of the 4ch RX front-end chip is 9 dB to 30 dB per channel. The LNA-PS chip consumes 82 mA, and the 4ch RX front-end chip consumes 97 mA from a 1.2 V supply voltage. The chip sizes of the 2 × 2 LNA-PS and the 4ch RX front end are 2.39 mm × 1.3 mm and 2.42 mm × 1.62 mm, respectively.