• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.5
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• pp.79-84
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• 2017

This paper is a multi-input multi-path (Multiple-input multiple-output: MIMO) using a space-alternating generalized expectation maximization(SAGE) algorithm in the parameter channel and determine the channel estimation performance. Estimated by the algorithm, SAGE time-varying channel environment, the channel parameters estimated from the parameters of the channel measured in the island region 781 of the band in order to compare the performance and compares the original data. This allows you to check the performance of the algorithm SAGE and is highly stable to delay spread (Delay Spread), the diffusion angle of arrival (Arrive of Angular Spread) performance in terms of accuracy down through the SAGE algorithm for estimating a more general calculation parameters.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.87-89
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• 2005

This paper presents an optimal tuning method of the decentralized PI controller of the two-input, two-output(TITO) second order system with time-delay using LQR approach.

• Journal of Mechanical Science and Technology
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• v.18 no.8
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• pp.1297-1305
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• 2004

In this paper, we propose a new scheme for the discretization of nonlinear systems using Taylor series expansion and the zero-order hold assumption. This scheme is applied to the sampled-data representation of a non-affine nonlinear system with constant input time-delay. The mathematical expressions of the discretization scheme are presented and the ability of the algorithm is tested for some of the examples. The proposed scheme provides a finite-dimensional representation for nonlinear systems with time-delay enabling existing controller design techniques to be applied to them. For all the case studies, various sampling rates and time-delay values are considered.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.10
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• pp.1894-1899
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• 2010

This note is concerned with a robust sliding mode control(SMC) for a class of unmatched uncertain system with severe commensurate state time delay. The suggested method is extended to the control of severe state time delay systems with unmatched uncertainties except the matched input matrix uncertainty. A transformed sliding surface is proposed and a stabilizing control input is suggested. The closed loop stability together with the existence condition of the sliding mode on the proposed sliding surface is investigated through one Lemma and two Theorems by using the Lyapunov direct method with the concept of the control Lyapunov function instead of complex Lyapunov-Kravoskii functionals. Through an illustrative example and simulation study, the usefulness of the main results is verified.

• Journal of Institute of Control, Robotics and Systems
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• v.15 no.2
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• pp.121-127
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• 2009

This paper deals with the design problem of robust stabilization and non-fragile controller for discrete-time singular systems with parameter uncertainties and time-varying delays in state and input by delay-dependent Linear Matrix Inequality (LMI) approach. A new delay-dependent bounded real lemma for singular systems with time-varying delays is derived. Robust stabilization and robust non-fragile state feedback control laws are proposed, which guarantees that the resultant closed-loop system is regular, causal and stable in spite of time-varying delays, parameter uncertainties, and controller gain variations. A numerical example is given to show the validity of the design method.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.7
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• pp.1019-1023
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• 2012

This paper considers a model predictive control problem of discrete-time constrained systems with time-varying delay. For this problem, a delay dependent state feedback control approach is used to achieve asymptotic stabilization of systems with input constraints. Based on Lyapunov stability theory, a new stability condition is obtained via linear matrix inequality formulation to find cost monotonicity condition of the model predictive control algorithm which guarantee the closed loop stability. Finally, the proposed method is applied to a numerical example in order to show the effectiveness of our results.

• Journal of information and communication convergence engineering
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• v.2 no.2
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• pp.102-105
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• 2004

A Quadrature phase detector for high-speed delay-locked loop is introduced. The proposed Quadrature phase detector is composed of two nor gates and it determines if the phase difference of two input clocks is 90 degrees or not. The delay locked loop circuit including the Quadrature phase detector is fabricated in a 0.18 um Standard CMOS process and it operates at 5 GHz frequency. The phase error of the delay-locked loop is maximum 2 degrees and the circuits are robust with voltage, temperature variations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.2
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• pp.171-181
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• 1988

In this study, a packet voice/data terminal(PVDT) that services both voice and data in the packet-switched network is implemented. The software structure of the PVDT is designed according to the OSI 7 layer architecture. The discrimination of voice and data is made in the link layer. Voice packets have priority over data packets in order to minimize the transmission delay, and are serviced by a simple protocol so that the overhead arising form the retransmission of packets may be minimized. The hardware structure of the PVDT is divided into five modules; a master control module, a speech proessing module, a speech activity detection module, a telephone interface module, and an input/output interface module. In addition to the hardware implementation, the optimal reconstruction delay of voice packets to reduce the influence of delay variance is analyzed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.11
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• pp.2378-2384
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• 2009

A novel phase-locked loop(PLL) architecture of sub-micron locking time has been proposed. Input frequency is multiplied by using a delay-locked loop(DLL). The input frequency of a PLL is multiplied while the PLL is out of lock. The multiplied input frequency makes the PLL having a wider loop bandwidth. It has been simulated with a $0.18{\mu}m$ 1.8V CMOS process. The simulated locking time is $0.9{\mu}s$ at 162.5MHz and 2.6GHz, input and output frequency, respectively.

• The Journal of the Korea institute of electronic communication sciences
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• v.18 no.5
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• pp.777-784
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• 2023

A sense amplifier is an essential peripheral circuit for designing a memory and is used to sense a small differential input signal and amplify it into digital signal. In this paper, a high-speed sense amplifier applicable to in-memory computing circuits is proposed. The proposed circuit reduces sense delay time through transistor Mtail that provides an additional discharge path and improves the circuit performance of the sense amplifier by applying m-GDI (: modified Gate Diffusion Input). Compared with previous structure, the sense delay time was reduced by 16.82%, the PDP(: Power Delay Product) by 17.23%, the EDP(: Energy Delay Product) by 31.1%. The proposed circuit was implemented using TSMC's 65nm CMOS process, while its feasibility was verified through SPECTRE simulation in this study.