• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.5 s.347
• /
• pp.1-10
• /
• 2006

In this paper, an 1.8V 8-bit 500MSPS CMOS A/D Converter is proposed. In order to obtain the resolution of 8bits and high-speed operation, a Cascaded-Folding Cascaded-Interpolation type architecture is chosen. For the purpose of improving SNR, Cascaded-folding Cascaded-interpolation technique, distributed track and hold are included [1]. A novel folding circuit, a novel Digital Encoder, a circuit to reduce the Reference Fluctuation are proposed. The chip has been fabricated with a $0.18{\mu}m$ 1-poly 5-metal n-well CMOS technology. The effective chip area is $1050{\mu}m{\times}820{\mu}m$ and it dissipates about 146mW at 1.8V power supply. The INL and DNL are within ${\pm}1LSB$, respectively. The SNDR is about 43.72dB at 500MHz sampling frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.5 s.347
• /
• pp.54-63
• /
• 2006

This work proposes a 14b 100MS/s 0.18um CMOS ADC with optimized resolution, conversion speed, die area, and power dissipation to obtain the performance required in the fourth-generation mobile communication systems. The 3-stage pipeline ADC, whose optimized architecture is analyzed and verified with behavioral model simulations, employs a wide-band low-noise SHA to achieve a 14b level ENOB at the Nyquist input frequency, 3-D fully symmetric layout techniques to minimize capacitor mismatch in two MDACs, and a back-end 6b flash ADC based on open-loop offset sampling and interpolation to obtain 6b accuracy and small chip area at 100MS/s. The prototype ADC implemented in a 0.18um CMOS process shows the measured DNL and INL of maximum 1.03LSB and 5.47LSB, respectively. The ADC demonstrates a maximum SNDR and SFDR of 59dB and 72dB, respectively, and a power consumption of 145mW at 100MS/s and 1.8V. The occupied active die area is $3.4mm^2$.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.35S no.10
• /
• pp.144-155
• /
• 1998

The array weights that will maximize the SNR for any type of noise environment are determined by the function of the antenna design configuration and the directions of receiving target and interference signals. The conventional SLCs(sidelobe cancellers) using the SNR maximization perform worst from the saturation of the receiving system of main channel when the main antenna has pattern with high gain at the arrival angle of strong interference. In this paper, the new SLC is accomplished by using two independent antenna architecture. Main antenna is implemented with adaptive nulling, which is used for rejecting high-power interference primarily. Auxiliary antenna is realized with adaptive array for receiving interference signal to be suppressed completely, which has a characteristics of sufficient gain for every direction. The new SLC is implemented with above both antennas. We show that the new SLC, which consists of the adaptive nulling main antenna and the adaptive array auxiliary antenna, is useful in reducing the effect of strong interference like jammer, because the adaptive nulling at main antenna prevents its receiver and signal processor for saturation by strong interference. The proposed SLC has improved SNR over the conventional SLCs. The improved SNR at sidelobe region is typically more than 7 dB for a given test signal. Moreover, it improves the SNR of about 20 dB under strong interference at mainlobe.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.5 no.3
• /
• pp.210-219
• /
• 2005

We report on a low-cost V-band wireless transceiver with no use of any local oscillator in the receiver block using a self-heterodyne architecture. V-band millimeter-wave monolithic IC (MMIC) modules were developed to demonstrate the wireless transceiver using coplanar waveguide (CPW) and GaAs PHEMT technologies. The MMIC modules such as the MMIC low noise amplifier (LNA), medium power amplifier (MPA) and the up/down-mixer were installed in the transceiver system. To interface the MMIC chips with the component modules for the transceiver system, CPW-to-waveguide fin-line transition modules of WR-15 type were designed and fabricated. The fabricated LNA modules showed a $S_{21}$ gain of 8.4 dB and a noise figure of 5.6 dB at 58 GHz. The MPA modules exhibited a gain of 6.9 dB and a $P_{1dB}$ of 5.4 dBm at 58 GHz. The conversion losses of the up-mixer and the down-mixer module were 14.3 dB at a LO power of 15 dBm, and 19.7 dB at a LO power of 0 dBm, respectively. From the measurement of V-band wireless transceiver, a conversion gain of 0.2 dB and a $P_{1dB}$ of 5.2 dBm were obtained in the transmitter block. The receiver block showed a conversion gain of 2.1 dB and a $P_{1dB}$ of -18.6 dBm. The wireless transceiver system demonstrated a successful data transfer within a distance of 5 meters.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.8
• /
• pp.56-63
• /
• 2010

This work proposes a 12b 100MS/s 0.13um CMOS pipeline ADC for battery-powered mobile video applications such as DVB-Handheld (DVB-H), DVB-Terrestrial (DVB-T), Satellite DMB (SDMB), and Terrestrial DMB (TDMB) requiring high resolution, low power, and small size at high speed. The proposed ADC employs a three-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. A single shared and switched op-amp for two MDACs removes a memory effect and a switching time delay, resulting in a fast signal settling. A two-step reference selection scheme for the last-stage 6b FLASH ADC reduces power consumption and chip area by 50%. The prototype ADC in a 0.13um 1P7M CMOS technology demonstrates a measured DNL and INL within 0.40LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 60.0dB and a maximum SFDR of 72.4dB at 100MS/s, respectively. The ADC with an active die area of 0.92 $mm^2$ consumes 24mW at 1.0V and 100MS/s. The FOM, power/($f_s{\times}2^{ENOB}$), of 0.29pJ/conv. is the lowest of ever reported 12b 100MS/s ADCs.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.48 no.11
• /
• pp.44-52
• /
• 2011

In this article, we present a QoS-guaranteed IP mobility management scheme of Internet service for fast moving vehicles with multiple wireless network interfaces. The idea of the proposed mechanism consists of two things. One is that new wireless connections are established to available wireless channels whenever the measured data rate at the vehicle equipped with mobile gateway drops below to the required data rate of the user requirement. The other is that parallel distribution packet tunnels between an access router and the mobile gateway are dynamically constructed using multiple wireless network interfaces in order to guarantee the required data rate during the mobile gateway's movement. By doing these methods, the required data rate of the mobile gateway can be preserved while eliminating the possible delay and packet loss during handover operation, thus resulting in the guaranteed QoS. The architecture of the IETF standard HMIPv6 has been extended to realize the proposed scheme, and detailed algorithms for the extension of HMIPv6 has been designed. Finally, simulation has been done for performance evaluation, and the simulation results show that the proposed mechanism demonstrates guaranteed QoS during the handover with regard to the handover delay, packet loss and throughput.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.40 no.4
• /
• pp.191-202
• /
• 2017

The purpose of this study is to develop an engineer competency model using Analytical Hierarchy Process (AHP) to improve the national technical qualification system. Korea has managed technical human resources at the government level through the operation of a national technical qualification system that certifies engineers with national certificates or technical grades by laws. However, there have been increasing concerns that the government system is separated from global standards and does not reflect an engineer's comprehensive capabilities. For these reasons, the new architecture of the system has been continuously discussed and becomes a major policy issue of the Korean government. For the development of the engineer competency model, domestic and global models were separately structured using 554 valid questionnaires with a consistency ratio (CR) of 0.1 or less. The relative importance of engineer competency factors in a domestic model was career (0.383), qualification (0.253), academic degree (0.195), and job training (0.169) whereas the order in the global model was career (0.308), global ability (0.237), job training (0.175), domestic qualification (0.147), and academic degree (0.134). The results of AHP analysis indicated that the evaluation factors and methods recognized by engineers were different from a current government model focusing on domestic qualifications. There was also perceptual difference in the importance of engineer evaluation factors between groups depending on the type of organizations and markets. This means that it is necessary to reflect the characteristics of organizations and markets when evaluating engineer competency. Based on AHP analysis and literature reviews, this paper discussed how to develop a new engineer competency index (ECI) and presented two effective index models verified by simulation test using 59,721 engineers' information. Lastly, the paper discussed major findings of our empirical research and proposed policy alternatives for the improvement of a national engineer qualification system. The paper contributes to the management of technical human resources since it provides quantitative competency models that are objectively developed by reflecting market recognition and can be effectively used by the policy makers or firms.

• The KIPS Transactions:PartD
• /
• v.14D no.2
• /
• pp.265-272
• /
• 2007

In this paper, we implement an automated composition system of web services using hybrid techniques that merge the benefit of BPEL techniques, with the advantage of OWL-S, BPEL techniques have practical capabilities that fulfil the needs of the business environment such as fault handling and transaction management. However, the main shortcoming of these techniques is the static composition approach, where the service selection and flow management are done a priori and manually. In contrast, OWL-S techniques use ontologies to provide a mechanism to describe the web services functionality in machine-understandable form, making it possible to discover, and integrate web services automatically. This allows for the dynamic integration of compatible web services, possibly discovered at run time, into the composition schema. However, the development of these approaches is still in its infancy and has been largely detached from the BPEL composition effort. In this work, we describe the design of the SemanticBPEL architecture that is a hybrid system of BPEL4WS and OWL-S, and propose algorithms for web service search and integration. In particular, the SemanticBPEL has been implemented based on the open source tools. The proposed system is compared with existing BPEL systems by functional analysis. These comparisions show that our system outperforms existing systems.

• The KIPS Transactions:PartD
• /
• v.15D no.6
• /
• pp.755-766
• /
• 2008

Recently, NAND flash memory is becoming into the spotlight as a next-generation storage device because of its small size, fast speed, low power consumption, and etc. compared to the hard disk. However, due to the distinct characteristics such as erase-before-write architecture, asymmetric operation speed and unit, disk-based systems and applications may result in severe performance degradation when directly implementing them on NAND flash memory. Especially when a B-tree is implemented on NAND flash memory, intensive overwrite operations may be caused by record inserting, deleting, and reorganizing. These may result in severe performance degradation. Although ${\mu}$-tree has been proposed in order to overcome this problem, it suffers from frequent node split and rapid increment of its height. In this paper, we propose Log-Structured B-Tree(LSB-Tree) where the corresponding log node to a leaf node is allocated for update operation and then the modified data in the log node is stored at only one write operation. LSB-tree reduces additional write operations by deferring the change of parent nodes. Also, it reduces the write operation by switching a log node to a new leaf node when inserting the data sequentially by the key order. Finally, we show that LSB-tree yields a better performance on NAND flash memory by comparing it to ${\mu}$-tree through various experiments.

• Korean Journal of Construction Engineering and Management
• /
• v.17 no.5
• /
• pp.78-88
• /
• 2016

Recently BIM technology has been expanded for using in construction project. However its spread has been delayed than the initial expectations, due to the high-cost of BIM infrastructure development, the lack of regulations, the lack of process and so forth. In design phase, especially, collaboration based on BIM system has being a key factor for successful next generation building project. Through the analysis of current research trend about IT technologies, virtualization and BIM service, data exchange such as drawing, 3D model, object data, properties using cloud computing and virtual server system is defined as a most successful solution. In various industrial fields, cloud computing technology is utilized as a promising solution which can reduce time and cost of hardware infrastructure. Among the cloud computing technology, VDI is receiving a great deal of attention from it market as an essential part cloud computing. VDI enables to host multiple individual virtual machines by using hypervisor. It has an advantage to easy main device management. Therefore, this study implements a step-by-step user's DaaS by analyzing the desktop resource data of the workers from Pre-design phase to Schematic design, Design develop and Construction design phase. It also develops BIM environment based on test of BIM modeler and designers in architectural design firm. The goal of the study is to enable the cloud computing BIM server. It provides cost saving, high-performance quality of working environment and cooperation's convenience and high security when doing BIM work in small and medium sized architectural design firm.