• Title/Summary/Keyword: in-memory file system

Search Result 241, Processing Time 0.03 seconds

Design of High-capacity NAND Flash File System supporting Sensor Data Collection (센서 데이터 수집을 위한 대용량 NAND 플래시 파일 시스템의 설계)

  • Han, Kyoung-Hoon;Lee, Ki-Hyeok;Han, Hyung-Jin;Han, Ji-Yean;Sohn, Ki-Rack
    • Journal of KIISE:Computing Practices and Letters
    • /
    • v.15 no.7
    • /
    • pp.515-519
    • /
    • 2009
  • As the application fields of sensor nodes are getting diverse these days, it is required to have a way of collecting various data that is suitable for these application fields. In the case that the real-time surveillance over the data is unnecessary, present data collecting methods, which collect and transfer the data directly, can cause a waste of energy and data loss, A new method that store the collected data in a local storage and acquire them by query later on is required for nonreal-time applications. NAND flash has energy efficiency and large capacity so it is suitable for sensor nodes, Sensor nodes support 4-10 KBytes small sized memory and it is hard to build an effective file system since NAND Flash doesn't support overwriting NAND flash. This paper discusses an implementation of NAND Flash file system in sensor node environments. The file system makes long-term data collecting possible by reducing transmission cost. It is expected that this file system will play a central role in sensor network environments as it can be applied to various fields which call for long term data collecting.

Design of an Intelligent Ambulatory Monitoring System Using Flash Memory Card (Flash Memory Card를 이용한 Intelligent Ambulatory Monitoring 시스템 설계)

  • Song, G.K.;Lee, K.J.;Yoon, H.R.
    • Proceedings of the KOSOMBE Conference
    • /
    • v.1997 no.05
    • /
    • pp.330-333
    • /
    • 1997
  • In this paper, we designed a low power and small-sized, light weighted intelligent ambulatory monitoring system using a flash memory card. The system's hardware specifications are as follows: 2 channels, 8bit/250Hz sampling rate, 20M byte storage capacity, a single-chip microcontroller (68HC11E9). To easily interface with PC based system, FFS(Flash File System) was used. We obtained the QRS detection rate of 99.14 through the evaluation with MIT/BIH database.

  • PDF

A study on development of CATIA V5 file security system using CAA (CAA를 이용한 CATIA V5 파일보안시스템 개발에 관한 연구)

  • Chae H.C.;Park D.S.;Byun J.H.
    • Proceedings of the Korean Society of Precision Engineering Conference
    • /
    • 2006.05a
    • /
    • pp.417-418
    • /
    • 2006
  • CATIA V5 is one of the most preferred softwares in product design for domestic and industrial use. But with the development of the IT industry, design data by CATIA V5 can easily be hacked and stolen especially via the internet and through assistance storage medium. The design data could be protected through executive, physical and technical security system. The best way to maintain confidentiality of data from unauthorized access is to have a cryptosystem of the technical security. In this paper, a cryptosystem for the protection of design data was being proposed. The memory contains the file information made by the New and Open function of CATIA V5. No error can be expected even if the file changed before of after the application of Save and Open function, A cryptosystem was constructed in CATIA V5 by inserting crypto algorithm before and after the I/O process. The encryption/decryption algorithm of each function was based on the complex cipher, which applied permutation cipher and transpose cipher. The file security system was programmed in CAA V5 and Visual C++.

  • PDF

A Study on Development of CATIA V5 File Security System Using CAA (CAA를 이용한 CATIA V5 파일보안시스템 개발에 관한 연구)

  • Chae, Hee-Chang;Park, Doo-Seob;Byun, Jae-Hong
    • Journal of the Korean Society for Precision Engineering
    • /
    • v.24 no.5
    • /
    • pp.77-81
    • /
    • 2007
  • CATIA V5 is one of the most preferred softwares in product design for domestic and industrial use. But with the development of the IT industry, design data by CATIA V5 can easily be hacked and stolen especially via the internet and through assistance storage medium. The design data could be protected through executive, physical and technical security system. the best way to maintain confidentiality of data from unauthorized access is to have a cryptosystem of the technical security. In this paper, a cryptosystem for the protection of design data was being proposed. The memory contains the file information made by the New and Open function of CATIA V5. No error can be expected even if the file changed before of after the application of Save and Open function. A cryptosystem was constructed in CATIA V5 by inserting crypto algorithm before and after the I/O process. The encryption/decryption algorithm of each function was based on the complex cipher, which applied permutation cipher and transpose cipher. The file security system was programmed in CAA V5 and Visual C++.

A Parallel Processing Technique for Large Spatial Data (대용량 공간 데이터를 위한 병렬 처리 기법)

  • Park, Seunghyun;Oh, Byoung-Woo
    • Spatial Information Research
    • /
    • v.23 no.2
    • /
    • pp.1-9
    • /
    • 2015
  • Graphical processing unit (GPU) contains many arithmetic logic units (ALUs). Because many ALUs can be exploited to process parallel processing, GPU provides efficient data processing. The spatial data require many geographic coordinates to represent the shape of them in a map. The coordinates are usually stored as geodetic longitude and latitude. To display a map in 2-dimensional Cartesian coordinate system, the geodetic longitude and latitude should be converted to the Universal Transverse Mercator (UTM) coordinate system. The conversion to the other coordinate system and the rendering process to represent the converted coordinates to screen use complex floating-point computations. In this paper, we propose a parallel processing technique that processes the conversion and the rendering using the GPU to improve the performance. Large spatial data is stored in the disk on files. To process the large amount of spatial data efficiently, we propose a technique that merges the spatial data files to a large file and access the file with the method of memory mapped file. We implement the proposed technique and perform the experiment with the 747,302,971 points of the TIGER/Line spatial data. The result of the experiment is that the conversion time for the coordinate systems with the GPU is 30.16 times faster than the CPU only method and the rendering time is 80.40 times faster than the CPU.

Dynamic Threshold based Even-wear Leveling Policies (동적 임계값을 이용한 메모리 소거)

  • Park, Je-Ho
    • Journal of the Semiconductor & Display Technology
    • /
    • v.6 no.2 s.19
    • /
    • pp.5-10
    • /
    • 2007
  • According to the advantageous features of flash memory, its exploitation and application in mobile and ubiquitous related devices as well as voluminous storage devices is being increased rapidly. The inherent properties that are determined by configuration of flash memory unit might restrict the promising expansion in its utilization. In this paper, we study policies based on threshold values, instead of using global search, in order to satisfy our objective that is to decrease the necessary processing cost or penalty for recycling of flash memory space at the same time minimizing the potential degradation of performance. The proposed cleaning methods create partitions of candidate memory regions, to be reclaimed as free, by utilizing global or dynamic threshold values. The impact of the proposed policies is evaluated through a number of experiments, the composition of the optimal configuration featuring the methods is tested through experiments as well.

  • PDF

A study on real-time communication of remote station in the distributed control system (분산 제어 시스템에서 원격 제어국의 실시간 통신에 관한 연구)

  • 김내진;김진태;박인갑
    • Journal of the Korean Institute of Telematics and Electronics A
    • /
    • v.31A no.10
    • /
    • pp.21-30
    • /
    • 1994
  • We discussed the Distributed Control System's design on preface and analyzed time of the real-time communication by using designed system. The DCS proposed in this thesis was implemented to network file system having recovery advantage and shared memory method to access file system of a Remote Station with ease. Also, this system minimized the network delay-time by using the real-time VME147 board. In implemented DCS, the performance analysis of real-time process of a Remote Station was done to get the total time for reak-tune communication from a Remote Station to the Central Station after terminating of process. For the analysis of system performance, we experiented by three steps. Firstly, we measuredthe processing the of LOOP function that real-time CPU convertes to-2,500~10.000 values from the input data of the Analog Interface Card. Secondly, we measured the processing time of the LOGIC function and the LOOP function. Lastly, we measured total processing time for communication from a Remote Station to the Centrol Station.

  • PDF

DPCM-Based Image Pre-Analyzer and Quantization Method for Controlling the JPEG File Size (JPEG 파일 크기를 제어하기 위한 DPCM 기반의 영상 사전 분석기와 양자화 방법)

  • Shin, Sun-Young;Go, Hyuk-Jin;Park, Hyun-Sang;Jeon, Byeung-Woo
    • Proceedings of the IEEK Conference
    • /
    • 2005.11a
    • /
    • pp.561-564
    • /
    • 2005
  • In this paper, we present a new JPEG (Joint Photograph Experts Group) compression architecture which compresses still image into fixed size of bitstream to use restricted system memory efficiently. The size of bitstream is determined by the complexity of image and the quantization table. But the quantization table is set in advance the complexity of image is the essential factor. Therefore the size of bitstream for high complexity image is large and the size for low complexity image is small. This means that the management of restricted system memory is difficult. The proposed JPEG encoder estimates the size of bitstream using the correlation between consecutive frames and selects the quantization table suited to the complexity of image. This makes efficient use of system memory.

  • PDF

An Analysis on the Performance of TRIM Commands on SSDs and its Application to the Ext4 File System (SSD에서의 TRIM 명령어 처리 성능 분석 및 Ext4 파일 시스템으로의 적용)

  • Son, Hyobong;Lee, Youngjae;Kim, Yongserk;Kim, Jin-Soo
    • KIISE Transactions on Computing Practices
    • /
    • v.21 no.1
    • /
    • pp.52-57
    • /
    • 2015
  • In this paper, we analyze the performance of the TRIM commands on various SSDs and, based on our analysis results, we enhance the performance of these TRIM commands in the Ext4 file system. We observed that the performance of the TRIM commands improves as the size of the LBA-range increases, the sector number is aligned and continuous or more LBA-ranges are notified via a single TRIM command. However, although the performance is better when multiple LBA-ranges are informed by a single TRIM command, the Ext4 file system issues a single TRIM command for every LBA-range. In this paper, we modify the Ext4 file system to convey at most 64 LBA-ranges per TRIM command. Evaluations through Filebench show that the performance of file deletion operations is improved by up to 35%.

An Efficient System Software of Flash Translation Layer for Large Block Flash Memory (대용량 플래시 메모리를 위한 효율적인 플래시 변환 계층 시스템 소프트웨어)

  • Chung Tae-Sun;Park Dong-Joo;Cho Sehyeong
    • The KIPS Transactions:PartA
    • /
    • v.12A no.7 s.97
    • /
    • pp.621-626
    • /
    • 2005
  • Recently, flash memory is widely used in various embedded applications since it has many advantages in terms of non-volatility, fast access speed, shock resistance, and low power consumption. However, it requires a software layer called FTL(Flash Translation Layer) due to its hardware characteristics. We present a new FTL algorithm named LSTAFF(Large State Transition Applied Fast flash Translation Layer) which is designed for large block flash memory The presented LSTAFF is adjusted to flash memory with pages which are larger than operating system data sector sizes and we provide performance results based on our implementation of LSTAFF and previous FTL algorithms using a flash simulator.