• Title/Summary/Keyword: in-circuit test

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Design and Implementation of Parabolic Speed Pattern Generation Pulse Motor Control Chip (포물선 가감속 패턴을 가지는 정밀 펄스 모터 콘트롤러 칩의 설계 및 제작)

  • Won, Jong-Baek;Choi, Sung-Hyuk;Kim, Jong-Eun;Park, Jone-Sik
    • Proceedings of the KIEE Conference
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    • 2001.11c
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    • pp.284-287
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    • 2001
  • In this paper, we designed and implemented a precise pulse motor control chip that generates the parabolic speed pattern. This chip can control step motor[1], DC servo[2] and AC servo motors at high speed and precisely. It can reduce the mechanical vibration to the minimum at the change point of a degree of acceleration. Because the parabolic speed pattern has the continuous acceleration change. In this paper, we present the pulse generation algorithm and the parabolic pattern speed generation. We verify these algorithm using visual C++. We designed this chip with VHDL(Very High Speed Integrated Circuit Hardware Description Language) and executed a logic simulation and synthesis using Synopsys synthesis tool. We executed the pre-layout simulation and post-layout simulation with Verilog-XL simulation tool. This chip was produced with 100 pins, PQFP package by 0.35 um CMOS process and implemented by completely digital logic. We developed the hardware test board and test program using visual C++. We verify the performance of this chip by driving the servo motor and the function by GUI(Graphic User Interface) environment.

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A New Fault-Based Built-In Self-Test Scheme for 1.8GHz RF Front-End (1.8GHz 고주파 전단부의 결함 검사를 위한 새로운 BIST 회로)

  • Ryu Jee-Youl;Noh Seok-Ho
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.6 s.336
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    • pp.1-8
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    • 2005
  • This paper presents a new low-cost fault-based Built-In Self-Test (BIST) scheme and technique for 1.8GHz RF receiver front end. The technique utilizes input impedance matching measurement. The BIST block and RF receiver front end are designed using 0.25m CMOS technology on a single chip. The technique is simple and inexpensive. The overhead of the BIST circuit is approximately $10\%$ of the total area of the RF front end.

Parallel I/O DRAM BIST for Easy Redundancy Cell Programming (Redundancy Cell Programming이 용이한 병렬 I/O DRAM BIST)

  • 유재희;하창우
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.12
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    • pp.1022-1032
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    • 2002
  • A multibit DRAM BIST methodology reducing redundancy programming overhead has been proposed. It is capable of counting and locating faulty bits simultaneously with the test. If DRAM cells are composed of n blocks generally, the proposed BIST can detect the state of no error, the location of faulty bit block if there is one error and the existence of errors in more than two blocks, which are n + 2 states totally, with only n comparators and an 3 state encoder. Based on the proposed BIST methodology, the testing scheme which can detect the number and locations of faulty bits with the errors in two or more blocks, can be easily implemented. Based on performance evaluation, the test and redundancy programming time of 64MEG DRAM with 8 blocks is reduced by 1/750 times with 0.115% circuit overhead.

A Study on Development of Scaled-down HVDC Model (HVDC의 축소형 모델 개발에 관한 연구)

  • Ahn, Jong-Bo;Yun, Jae-Young;Kim, Kook-Hun;Lee, Jong-Moo;Kim, Jong-Moon;Lee, Ki-Do
    • Proceedings of the KIEE Conference
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    • 1999.11b
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    • pp.219-221
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    • 1999
  • HVDC(High Voltage Direct Current) transmission system was constructed between Cheju island and mainland Haenam and has been operating commercially since 1998. But research activities in this area are not so much. That is caused by the facts that HVDC is large scale system and it is not so easy to implement and to test. Though such simulation tools as RTDS(Real Time Digital Simulator) and EMTDC can be useful, these have limitations for actual control and protective system design. Therefore scaled-down HVDC model was developed for the purpose of researches at operating technique, control and protection methods. The design of this model was based on real Cheju-Haenam HVDC system. And additionally faults simulator such as ground fault, short-circuit and change of impedance in transmission line is equipped for analysis of these faults. Control system of the model was implemented fully digitally. So it is very easy for the researchers to develope control and protection algorithm and to test the performance.

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Enhanced Approach Using Computational and Experimental Method for the Analysis of Loudspeaker System

  • Park Seok-Tae
    • The Journal of the Acoustical Society of Korea
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    • v.24 no.3E
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    • pp.90-98
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    • 2005
  • Enhanced approach using computational and experimental method is proposed and performed to describe very well the behavior of loudspeaker than conventional method. Proposed procedure is composed of four parts. First, Thiele-Small parameters for test loudspeaker are identified by an electrical impedance method like as a delta mass method. Second part includes the processes to measure physical properties. Physical data like masses and thicknesses of loudspeaker's components are measured by an electrical precision scale and a digital vernier caliper. Third, the identified Thiele-Small parameters are proposed to be used as load boundary conditions for vibration analysis instead of electromagnetic circuit analysis to get a driving force upon bobbin part. Also, these parameters and physical data are used to modify physical properties required for computation to accommodate simulated sound pressure level with measured one for loudspeaker enclosure system. These data like as Young's modulus and thickness for a diaphragm are required for vibration analysis of loudspeaker but not measured accurately. Finally, it was investigated that simulated sound pressure level with full acoustic modeling including an acoustic port for test loudspeaker agreed with experimental result very well in the midrange frequency band(from 100 Hz to 2,000 Hz). In addition, several design parametric study is performed to grasp acoustical behaviors of loudspeaker system due to variations of diaphragm thicknesses and shapes of dust cap.

Effects of Alloying Elements on the Corrosion Layer Formation of Pb-Grid/Active Materials Interface (Pb 기판/활물질 계면의 부식층형성에 미치는 합금원소영향)

  • Oh, Se-Woong;Choe, Han-Cheol
    • Journal of Surface Science and Engineering
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    • v.40 no.5
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    • pp.225-233
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    • 2007
  • Effects of alloying elements on the corrosion layer formation of Pb-grid/active materials interface has been researched for improvement of corrosion resistance of Pb-Ca alloy. For this research, various amounts of alloying elements such as Sn, Ag and Ba were added to the Pb-Ca alloys and investigated their corrosion behaviors. Batteries fabricated by using these alloys as cathode grids were subjected to life cycle test. Overcharge life cycle test was carried out at $75^{\circ}C$, 4.5 A, for 110 hrs. with KS standard (KSC 8504). And then, after keeping the battery with open circuit state for 48 hr, discharge was carried out at 300A for 30 sec. Corrosion morphology and interface between Pb-grid and active materials were investigated by using ICP, SEM, WDX, and LPM. Corrosion layer of Pb-Ca alloy got thicken with increasing Ca content. For Pb-Ca-Sn alloy, thickness of corrosion layer decreased as Sn and Ag content increased gradually. In case of Pb-Ca-Sn-Ba alloy, thickness of corrosion layer decreased up to 0.02 wt% Ba addition, whereas, it was not changed in case of above 0.02 wt% Ba addition.

Effects of Underfills on the Dynamic Bending Reliability of Ball Grid Array Board Assembly (Ball Grid Array 보드 어셈블리의 동적굽힘 신뢰성에 미치는 언더필의 영향)

  • Jang, Jae-Won;Bang, Jung-Hwan;Yoo, Se-Hoon;Kim, Mok-Soon;Kim, Jun-Ki
    • Korean Journal of Materials Research
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    • v.21 no.12
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    • pp.650-654
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    • 2011
  • In this paper, the effects of conventional and newly developed elastomer modified underfill materials on the mechanical shock reliability of BGA board assembly were studied for application in mobile electronics. The mechanical shock reliability was evaluated through a three point dynamic bending test proposed by Motorola. The thermal properties of the underfills were measured by a DSC machine. Through the DSC results, the curing condition of the underfills was selected. Two types of underfills showed similar curing behavior. During the dynamic bending reliability test, the strain of the PCB was step increased from 0.2% to 1.5% until the failure circuit was detected at a 50 kHz sampling rate. The dynamic bending reliability of BGA board assembly using elastomer modified underfill was found to be superior to that of conventional underfill. From mechanical and microstructure analyses, the disturbance of crack propagation by the presence of submicron elastomer particles was considered to be mainly responsible for that result rather than the shear strength or elastic modulus of underfill joint.

Effects of phosphating bath compositions on the formation and structure of zinc phosphate conversion coatings on magnesium alloy AZ31

  • Phuong, Nguyen Van;Lee, Kyuhwan;Chang, Doyon;Moon, Sungmo
    • Proceedings of the Korean Institute of Surface Engineering Conference
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    • 2012.05a
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    • pp.322-323
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    • 2012
  • This study discussed the formation of phosphate conversion coatings on AZ31 Mg alloy (AZ31) from the zinc phosphating bath with various concentrations of sodium fluoride (NaF). The effects of NaF on the formation, structure, composition and electrochemical behavior of the phosphate coatings were examined using scanning electron microscopy (SEM), X-ray diffraction (XRD) weight balances, open circuit potential (OCP) transients, potentiodynamic polarization curves and immersion test. The coatings were composed of two layers: an outer $Zn_2(PO_4)_3.4H_2O$ (hopeite) crystal layer and an inner amorphous of $MgZn_2(PO_4)_2$. NaF concentration is emphasized to be highly effective in the formation of the hopeite crystal and etching and coating rates. Potentiodynamic polarization and immersion test showed that the coatings formed in the zinc phosphating bath with addition of NaF have much higher corrosion resistance than bare AZ31.

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Numerical and Experimental Analyses of a Hot-Wire Gas Flowmeter

  • Kim, Byoung-Chul;Joung, Ok-Jin;Kim, Young-Han
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1201-1206
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    • 2003
  • A measurement device for gas flow rate using hot-wire module is developed for the utilization in low-accuracy industrial applications. The module has three wires of measuring and heating, and a bridge circuit is installed to detect electric current through the wire in the module. An amplification of the signal and conversion to digital output are conducted for the online measurement with a personal computer. In addition, temperature distribution in the module is numerically analyzed to examine the measured outcome from the module experiment. The flow rate of air and carbon dioxide gas is separately measured for the performance examination of the device. The experimental relation of measurement and flow agrees with the prediction from the numerical analysis. The outcome of the performance test indicates that the accuracy and reproducibility of the module is satisfactory for the purpose of industrial applications.

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The Design of Path Length Controller in Ring Laser Gyroscope for Attitude Control in the space launch vehicle (우주발사체 자세제어용 링 레이저 자이로 피에조 구동기 설계)

  • Kim, Eui-Chan;Yang, Koon-Ho
    • Aerospace Engineering and Technology
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    • v.9 no.2
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    • pp.31-35
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    • 2010
  • The Ring Laser Gyroscope makes use of the Sagnac effect within a resonant ring cavity of a He-Ne laser and has more accuracy than the other gyros. The space launch vehicle use require the high accuracy Gyro to control and determine the altitude to deliver the satellite in the space. In this paper, The theory of the Path Length Control is explained. The electrical design of Path Length Controller is described. The Design for Path Length Controller is composed of the demodulator, integrator, phase shifter, high voltage amplifier. We apply the circuit to 28cm square ring laser gyro and get the test results.