• The Journal of the Acoustical Society of Korea
• /
• v.20 no.1E
• /
• pp.14-19
• /
• 2001

We have proposed BIST method and circuit for embedded 16M SDRAM with logic. It can test the AC parameter of embedded 16M SDRAM using the BIST circuit capable of detecting the address of a fail cell installed in an Merged Memory with Logic(MML). It generates the information of repair for redundancy circuit. The function and AC parameter of the embedded memory can also be tested using the proposed BIST method. It is possible to test the embedded SDRAM without external test pin. The total gate of the BIST circuit is approximately 4,500 in the case of synthesizing by 0.25μm cell library and is verified by Verilog simulation. The test time of each one AC parameter is about 200ms using 2Y-March 14n algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.17 no.7
• /
• pp.666-676
• /
• 1992

In this paper, algorithm and testable circuit to find all PSF(Pattern Sensitive Fault ) occured in RAM were proposed. Conventional test circuit and algorithm took much time in testing because consecutive test for RAM cells or f-dimensional memory struciure was not employed. In this paper, methodology for parallel RAM-testing was proposed by compensating additional circuit for test to conventional RAM circuit. Additional circuits are parallel comparator, error detector, group selector circuit and a modified decoder used for parallel testing. And also, the constructive method of Eulerian path to obtain efficient test pattern was performed. Consequently, If algorithm proposed in this paper Is used, the same operations as 32sxwor4 lines will be needed to test b x w=n matrix RAM. Circuit simulation was performerd, and 10 bits x :If words testable RAM was designed.

• The Transactions of the Korean Institute of Electrical Engineers D
• /
• v.54 no.4
• /
• pp.243-250
• /
• 2005

Test methodology is diversity by devices and the number of test pattern is tremendous because the digital circuit includes TTL and CMOS family ICs as well as high density devices such as ROM and RAM. Accordingly, the quick and effective test strategy is required to enhance the test productivity. This paper proposes the test strategy which is able to be applied efficiently to the diversity devices on the digital circuit board by analyzing the structure and characteristic of the digital device. Especially, this test strategy detects the faulted digital device or the faulted digital circuit on the digital board using SSA(Serial Signature Analysis) technique based on the polynomial division theory The SSA technique identifies the faults by comparing the reminder from good device with reminder from the tested device. At this time, the reminder is obtained by enforcing the data stream obtained from output pins of the tested device on the LFSR(Linear Feedback Shift Register) representing the characteristic equation. Also, the method to obtain the optimal signature analysis circuit is explained by furnishing the short bit input streams to the long bit input streams to the LFSR having 8, 12, 16, 20bit input/output pins and by analyzing the occurring probability of error which is impossible to detect. Finally, the effectiveness of the proposed test strategy is verified by simulating the stuck at 1 errors or stuck at 0 errors for several devices on typical 8051 digital board.

• Journal of Institute of Control, Robotics and Systems
• /
• v.3 no.3
• /
• pp.323-331
• /
• 1997

A new probing mechanism and an active compliance control algorithm have been developed for the in-circuit test of a PCB( printed circuit board ). Commercially available robotic probing devices are incapable of controlling contact force generated through rigid probe contacts with a solder joint, at high speed. The uncontrollable excessive contact force often brungs about some defects on the surface of the solder joint, which is plastically deformable over some limited contact force. This force also makes unstable contact motions resulting in unreliable test data. To overcome these problems, we propose that a serially connected macro and micro device with active compliance provide the best potential for a safe and reliable in-circuit test. This paper describes the design characteristics, modeling and control scheme of the newly proposed device. The experimental results clearly show the effectiveness of the proposed system.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.35C no.4
• /
• pp.30-37
• /
• 1998

In this paper, we propose a test generation method for large scale sequential circuits based on circuit partitioning to increase the size of circuits that the implicit product machine traversal (IPMT) method can handle. Our method paratitions a circuit under test into subset circuits with only single output, and performs a partial scan design using the state transtition cost that represents a degree of the connectivity of the subset circuit. The IPMT method is applied to the partitioned partial scan circuits in test generation. Experimental results for ISCAS89 benchmark circuits with more thatn 50 flip-flops show that our method has generated test patterns with almost 100% fault coverage at high speed by use of 34%-73% scanned flip-flops.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.25 no.6
• /
• pp.75-81
• /
• 2011

This study aims to research and analyze the cause and countermeasures of the short-circuit test failures of the distribution transformer, which captures failure share at the highest level when carrying out its performance test. For this purpose, the research was done on the basis of 77 failure cases out of 998 tests in total performed by the Korea Electrotechnology Research Institute(KERI) from 2004 to 2010. Based on the research, the paper also includes analysis of the causes of the short-circuit test failures in its early stage of transformer development and proposes its countermeasures accordingly.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.9 no.3
• /
• pp.335-342
• /
• 2014

In this paper We study on test methods and procedures for Hybrid Track Circuit's practicalization. It's possible to apply to HTC's Seoulmetro and high-speed train by proposing test method considering special rail environment and RFID tag and leader, antenna We also present the test methods and procedures for safe and reliable of interface among the Hybrid track circuit devices.

• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.56 no.9
• /
• pp.1566-1570
• /
• 2007

[ $SF_6$ ] gas circuit breakers are widely used for short circuit current interruption in EHV(Extra High Voltage) or UHV(Ultra High Voltage) power systems. To develop $SF_6$ gas circuit breakers, the arc resistance value is necessary to compare experimental results to numerical ones. The arc resistance value can be obtained from a breaking test with a $SF_6$ gas circuit breaker. The direct testing or synthetic testing facility is widely used to verify the breaking ability for $SF_6$ gas circuit breakers. We employed the simplified synthetic testing facility to test a $SF_6$ gas circuit breaker prototype. The arc resistance characteristic was measured and calculated under the various experimental conditions. This arc resistance value can be used for verifying the numerical results from arc simulation in a circuit breakers.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.1
• /
• pp.286-292
• /
• 2014

This paper presents the parameters optimization technology for generating the first short stroke lightning current waveform($10/350{\mu}s$) which is necessary for the performance tests of components of lightning protection systems, as required under IEC 62305 and the newly amended IEC 62561. The circuit using the crowbar device specified in IEC 62305 was applied to generate the lightning current waveform. To find the proper parameters of the circuit is not easy because the circuit consists of two parts; circuit I, which relates to the front of current waveform, and circuit II, which relates to the tail. A simulation in PSpise was carried out to find main factors related to the front and tail of $10/350{\mu}s$. The lightning current generator was developed by utilizing the circuit parameters found in the simulation. In the result of experiments, new parameters of the circuits need to be changed because of the difference between the simulation and the experiment results. Using the iterative method, the optimized parameters of the circuits was determined. Also a multistage-type external coil and a damping resistor were proposed to make the efficiency of generation to enhance. According to the result in this paper, an optimized first short stroke lightning current waveform was obtained.

• ETRI Journal
• /
• v.28 no.2
• /
• pp.182-190
• /
• 2006

The circuit modeling of interdigitated capacitors fabricated by high-k low-temperature co-fired ceramic (LTCC) sheets was investigated. The s-parameters of each test structure were measured from 50 MHz to 10 GHz, and the modeling was performed using these measured sparameters up to the first resonant frequency. Each test structure was divided into appropriate building blocks. The equivalent circuit of each building block was composed based on the partial element equivalent circuit (PEEC) method. Modeling was executed to optimize the parameters in the equivalent circuit of each building block. The validity of the extracted parameters was verified by the predictive modeling for the test structures with different geometry. After that, Monte Carlo analysis and sensitivity analysis were performed based on the extracted parameters. The modeling methodology can allow a device designer to improve the yield and to save time and cost for the design and manufacturing of devices.