• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.78-84
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• 1984

We propose a new algorithm which detects stuck-open faults in CMOS circuits without being affected by time skews not using additional circuits. That is, the Domino CMOS circuit structure is used as circuit configurations and the clocking gate in this circuit is modeled as one branch, then test sequence is generated by using the transition test. Also, it is verified by applying this algorithm implemented in VAX II/780 to arbitrary CMOS circuits that all of stuck-open faults which were not detected because of time skews in conventional methods is detected.

• Journal of information and communication convergence engineering
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• v.11 no.1
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• pp.56-61
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• 2013

Modern integrated circuits (ICs) are becoming an integrated parts of analog, digital, and radio frequency (RF) circuits. Testing these RF circuits on a chip is an important task, not only for fabrication quality control but also for tuning RF circuit elements to fit multi-standard wireless systems. In this paper, RF test circuits suitable for embedded testing are introduced: RF power detectors, power control circuits, directional couplers, and six-port reflectometers. Various types of embedded RF power detectors are reviewed. The conventional approach and our approach for the RF power control circuits are compared. Also, embedded tunable active directional couplers are presented. Then, six-port reflectometers for embedded RF testing are introduced including a 77-GHz six-port reflectometer circuit in a 130 nm process. This circuit demonstrates successful calibrated reflection coefficient simulation results for 37 well distributed samples in a Smith chart. The details including the theory, calibration, circuit design techniques, and simulations of the 77-GHz six-port reflectometer are presented in this paper.

• Journal of Power Electronics
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• v.17 no.2
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• pp.561-569
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• 2017

Power converter design requires simulation accuracy. In addition to the requirement of accurate models of power semiconductor devices, this paper highlights the role of considering a very good description of the converter circuit layout for an accurate simulation of its electrical behavior. This paper considers a simple experimental circuit including one switching cell where a MOSFET transistor controls the diode under test. The turn-off transients of the diode are captured, over which the circuit wiring has a major influence. This paper investigates the necessity for accurate modeling of the experimental test circuit wiring and the MOSFET transistor. It shows that a simple wiring inductance as the circuit wiring representation is insufficient. An adequate model and identification of the model parameters are then discussed. Results are validated through experimental and simulation results.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.8 no.1
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• pp.36-39
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• 2009

In this paper, we propose a 4-wire type driving circuit for resistive touch panel which was manufactured at the lab. The circuit is designed by using the touch panel controller ADS7846 and AVR microcontroller board. The test result shows that the designed circuit can give and transmit the position information of touch panel to the computer.

• Proceedings of the KIEE Conference
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• 2003.10b
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• pp.63-65
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• 2003

In the case of the large motors which can't direct load tests, IEEE 112 equivalent circuit test was selected instead of the circle diagram method in the newly KEPIC's code. According to the change of code, Hyosung established an equivalent circuit test method based on Standard IEEE 112. In this paper, we compared the test results between IEEE 112 and other standards, CSA C-390, JEC2137 for the large motors.

• Journal of the Korea Society of Computer and Information
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• v.4 no.1
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• pp.28-37
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• 1999

In this paper. we developed a delay test architecture and test procedure for clocked 5-bit asynchronous counter circuit based on boundary scan architecture. To develope, we analyze the problems of conventional method on delay test for clocked sequential circuit in boundary scan architecture. This paper discusses several problems of delay test on boundary scan architecture for clocked sequential circuit. Conventional test method has some problems of improper capture timing, of same pattern insertion, of increase of test time. We suggest a delay test architecture and test procedure, is based on a clock count-generation technique to generate continuous clocks for clocked input of CUT. The simulation results or 5-bit counter shows the accurate operation and effectiveness of the proposed delay test architecture and procedure.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.5
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• Journal of Korea Entertainment Industry Association
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• v.13 no.6
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• pp.165-173
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• 2019

This study aims to examine the moderating effects of band circuit training for the mortality improvement of elderly women to provide an effective exercise moderating program for the enhanced quality of life of the elderly. To achieve the purpose of this study, the moderating effects of 8 weeks of band circuit training in the Senior Fitness Tests (SFT) and Sitting Rising Tests (SRT) of elderly women ages 65 and older in Y city were examined and the following results were gained. The functional fitness of elderly women according to the moderating effects of band circuit training (sitting down in a chair and standing up, lifting 2 kg dumbbells, walking in place for 2 minutes, sitting in a chair and bending forward, hand holding behind one's back, walking back and forth for 2.44 m) and the Sitting Rising Test (SRT) displayed statistically significant interaction effects among measurement times and groups and positive improvements were shown in the test group after band circuit training moderation. These research results show that band circuit training moderation has a positive effect on functional fitness and SRT, which are associated with the mortality rate of the elderly, and thus it can be applied as an effective exercise moderation program for the improvement of quality of life through the mortality improvement of the elderly.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.995-998
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• 2005

This paper proposes a new SoC (System-on-Chip)-based automatic compensation circuit (ACC) for 5GHz low noise amplifier (LNA). This circuit is extremely useful for today's RF IC (Radio Frequency Integrated Circuit) devices in a complete RF transceiver environment. The circuit contains RF BIST (Built-ln Self-Test) circuit, Capacitor Mirror Banks (CMB) and digital processing unit (DPU). The ACC automatically adjusts performance of 5GHz LNA by the processor in the SoC transceiver when the LNA goes out of the normal range of operation.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.12
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• pp.36-46
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• 2008

This paper is to study on the Construction of Test circuit and Unification of Experiment Method for high voltage gas-insulated load switch using high power testing system The high power testing system is a equipment to verify electrical and mechanical performance on electrical product. The system consist of short-circuit generator, back-up breaker, making switch, impedance, high voltage transformer, low voltage transformer, measuring and protection system, etc. Using this system, we can test related to high power, for example, short-time current test, active load Current test, magnetizing Current test, capacitive current test, closed loop current test, etc. Standards of high voltage gas-insulated load switch that is in use domestic distribution line are ES 5925-0002, IEC 60265-1, IEC 62271-1 and IEEE C 37.74, etc. In this paper, we standardized on the test procedure, organization of test circuit and analysis of measured data prescribed many difference standards, and applied this test method to 600[MVA] high power testing system. So that we can test the load switch satisfied standards.