• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.4
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• pp.382-391
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• 2005

Increasing of the nonlinear type power electronics equipment, power conditioning systems (PCS) have been researched and developed for many years in order to compensate for harmonic disturbances and reactive power. PCS's not only improve harmonic current and power factor in the ac grid line but also achieves energy saving used by the renewable energy source (RES). In this paper, the implementation of a current controlled voltage source inverter (CCVSI) using RES for PCS is presented. The basic principle and control algorithm is theoretically analyzed and the design methodology of the system is discussed. The proposed system could achieve power quality control (PQC) to reduce harmonic current and improve power factor, and demand side management (DSM) to supply active power simultaneously, which are both operated by the polarized ramp time (PRT) current control algorithm and the grid-interactive current control algorithm. A 1KVA test model of the CCVSI has been built using IGBT controlled by a digital signal processor (DSP). To verify the proposed system, a comprehensive evaluation with theoretical analysis, simulation and experimental results is presented.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5422-5441
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• 2016

Despite the abundant literature in the field, there is still the need to find a time-efficient, highly accurate, easy to deploy and robust localization algorithm for real use. The algorithm only involves minimal human intervention. We propose an enhanced Received Signal Strength Indicator (RSSI) based positioning algorithm for Wi-Fi capable devices, called the Dynamic Weighted Evolution for Location Tracking (DWELT). Due to the multiple phenomena affecting the propagation of radio signals, RSSI measurements show fluctuations that hinder the utilization of straightforward positioning mechanisms from widely known propagation loss models. Instead, DWELT uses data processing of raw RSSI values and applies a weighted posterior-probabilistic evolution for quick convergence of localization and tracking. In this paper, we present the first implementation of DWELT, intended for 1D location (applicable to tunnels or corridors), and the first step towards a more generic implementation. Simulations and experiments show an accuracy of 1m in more than 81% of the cases, and less than 2m in the 95%.

• Journal of Digital Contents Society
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• v.5 no.3
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• pp.205-212
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• 2004

This paper presents a design and implementation example of intelligent society member management system that is constructed to induce various research activity. Based on members data and society activity record, the system executed data mining. In the process of data mining useful society activity rules was produced and in result members could effectively interact with the system. Decision Tree Algorithm was used in the process, which is one of the methods of data mining. We presemts a plan for personalization website to provide user oriented administration policy and dynamic interface by using analyzed information of society activity rules produced.

• ETRI Journal
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• v.19 no.3
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• pp.228-241
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• 1997

In this paper, we present a design of modem and vocoder digital signal processor (DSP) chips for CDMA mobile station. The modem chip integrates CDMA reverse link modulator, CDMA forward link demodulator and Viterbi decoder. This chip contains 89,000 gates and 29 kbit RAMs, and the chip size is $10 mm{\times}10.1 mm$ which is fabricated using a $0.8{\mu}m$ 2 metal CMOs technology. To carry out the system-level simulation, models of the base station modulator, the fading channel, the automatic gain control loop, and the microcontroller were developed and interfaced with a gate-level description of the modem application specific integrated circuit (ASIC). The Modem chip is now successfully working in the real CDMA mobile station on its first fab-out. A new DSP architecture was designed to implement the Qualcomm code exited linear prediction (QCELP) vocoder algorithm in an efficient way. The 16 bit vocoder DSP chip has an architecture which supports direct and immediate addressing modes in one instruction cycle, combined with a RISC-type instruction set. This turns out to be effective for the implementation of vocoder algorithm in terms of performance and power consumption. The implementation of QCELP algorithm in our DSP requires only 28 million instruction per second (MIPS) of computation and 290 mW of power consumption. The DSP chip contains 32,000 gates, 32K ($2k{\times}16\;bit$) RAM, and 240k ($10k{\times}24\;bit$) ROM. The die size is $8.7\;mm{\times}8.3\;mm$ and chip is fabricated using $0.8\;{\mu}m$ CMOS technology.

• Journal of Ocean Engineering and Technology
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• v.24 no.3
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• pp.46-51
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• 2010

This paper describes the implementation of a precise underwater navigation solution using a multi-sensor fusion technique based on USBL, DVL, and IMU measurements. To implement this precise underwater navigation solution, three strategies are chosen. The first involves heading alignment angle identification to enhance the performance of a standalone dead-reckoning algorithm. In the second, the absolute position is found quickly to prevent the accumulation of integration error. The third one is the introduction of an effective outlier rejection algorithm. The performance of the developed algorithm was verified with experimental data acquired by the deep-sea ROV, Hemire, in the East-sea during a survey of a methane gas seepage area at a 1,500 m depth.

• Journal of IKEEE
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• v.24 no.1
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• pp.243-247
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• 2020

As the autonomous driving market is rapidly growing, research on autonomous driving is being conducted. Self-driving functions should be performed regardless of the weather for the driver's safety. However, misty weather is difficult to autonomous driving because of the lack of visibility, so a defog algorithm should be used. The image obtained through the fog removal algorithm causes the image quality to deteriorate. To improve this problem, HSV color correction is used to increase the sharpness. In this paper, we propose a color correction hardware using HSV that can cope with 4K images. The hardware was designed with Verilog and verified by Modelsim. In addition, the FPGA was implemented with the goal of Xilinx's xc7z045-2ffg900.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.466-468
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fired length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine

• Journal of Convergence Society for SMB
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• v.3 no.1
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• pp.31-41
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• 2013

There have been various recent methods proposed in detecting driver drowsiness (DD) to avert fatal accidents. This work proposes a hardware/software (HW/SW) co-design approach in implementation of a DD detection system adapted from an AdaBoost-based object detection algorithm with Haar-like features [1] to monitor driver's eye closure rate. In this work, critical functions of the DD detection algorithm is accelerated through custom hardware components in order to speed up processing, while the software component implements the overall control and logical operations to achieve the complete functionality required of the DD detection algorithm. The HW/SW architecture was implemented on an Altera DE2 board with a video daughter board. Performance of the proposed implementation was evaluated and benchmarked against some recent works.

• Journal of the Optical Society of Korea
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• v.17 no.5
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• pp.362-370
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• 2013

In this paper, we propose a novel optical implementation of a 3DES algorithm based on dual XOR logic operations for a cryptographic system. In the schematic architecture, the optical 3DES system consists of dual XOR logic operations, where XOR logic operation is implemented by using a free-space interconnected optical logic gate method. The main point in the proposed 3DES method is to make a higher secure cryptosystem, which is acquired by encrypting an individual private key separately, and this encrypted private key is used to decrypt the plain text from the cipher text. Schematically, the proposed optical configuration of this cryptosystem can be used for the decryption process as well. The major advantage of this optical method is that vast 2-D data can be processed in parallel very quickly regardless of data size. The proposed scheme can be applied to watermark authentication and can also be applied to the OTP encryption if every different private key is created and used for encryption only once. When a security key has data of $512{\times}256$ pixels in size, our proposed method performs 2,048 DES blocks or 1,024 3DES blocks cipher in this paper. Besides, because the key length is equal to $512{\times}256$ bits, $2^{512{\times}256}$ attempts are required to find the correct key. Numerical simulations show the results to be carried out encryption and decryption successfully with the proposed 3DES algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.718-723
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.