• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.31-37
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• 2009

This paper presents an efficient frame synchronization strategy with the identification of modulation type for Digital Video Broadcasting-Satellite second generation (DVB-S2). To detect the Start Of Frame (SOF) and identify a modulation mode at low SNR, we propose a new correlator structure and a low complexity Automatic Gain Controller (AGC). The proposed frame synchronization architecture can reduce about 93% multipliers and 89% adders compared with the direct implementation of the Differential - Generalized Post Detection Integration (D-GPDI) algorithm which is very complex and the proposed a low complexity AGC consists of only 5 multipliers and 3 adders. The proposed architecture has been thoroughly verified on the Xilinx Virtex II FPGA board.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.44 no.3
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• pp.108-123
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• 2007

As H.264/AVC standard has proven to be a key technology of multimedia application, many researches to improve H.264/AVC standard are actively conducted. Those researches are conducted in various ways such as algorithm analysis and improvement or structure enhancement for reducing bottlenecks of performance. Even though targets and directions of those studies are not the same, performance of H.264/AVC standard is commonly analyzed in the early phase. In analysis phase, potential problems with H.264/AVC standard are identified and the most critical problem which has serious effects on performance is determined. Therefore, analysis phase is one of the important steps to decide overall directions and targets of the research. This research proposes a mathematical model which can be used in the early performance analysis phase to estimate performance in conducting research of improving the performance of H.264/AVC Baseline Profile decoder. The proposed model is designed by considering many variables of H.264/AVC decoder operation so that it is easy to predict its performance according to changes in each element.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.34-42
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• 2014

This paper presents a low-complexity and high-throughput symbol detector for two-spatial-stream multiple-input multiple-output systems based on the modified maximum-likelihood symbol detection algorithm. In the proposed symbol detector, the cost function is calculated incrementally employing a multi-cycle architecture so as to eliminate the complex multiplications for each symbol, and the slicing operations are performed hierarchically according to the range of constellation points by a pipelined architecture. The proposed architecture exhibits low hardware complexity while supporting complicated modulations such as 256 QAM. In addition, various modulations and antenna configurations are supported flexibly by reconfiguring the pipeline for the slicing operation. The proposed symbol detector is implemented with 38.7K logic gates in a $0.11-{\mu}m$ CMOS process and its throughput is 166 Mbps for $2{\times}$3 16-QAM and 80Mbps for $2{\times}3$ 64-QAM where the operating frequency is 478 MHz.

• Journal of IKEEE
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• v.14 no.3
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• pp.244-249
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• 2010

We fabricated optical sensor system that take a measurement particles using a line-CCD in ocean. To measure particles, we used 680nm laser diode which is appropriate. we tested to operate optical system in water tank and ocean. It has performance that detected signal of sensors transfer microprocessor, FPGA as long as move up and down it's motion. The system algorithm also analysis output -pressure, temperature, particle numbers in depth.-For experiment, our particle sensor system has high accuracy counter. therefore, we proposed that a line-CCD is available on optical sensor system in ocean.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.65-73
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• 2002

In this paper, we propose and verify an implementation method for a single-chip 2048 complex point FFT/IFFT in terms of sequential data processing. For the sequential processing of 2048 complex data, buffers to store the input data are necessary. Therefore, DRAM-like pipelined commutator architecture is used as a buffer. The proposed structure brings about the 60% chip size reduction compared with conventional approach by using this design method. The 16-point FFT is a basic building block of the entire FFT chip, and the 2048-point FFT consists of the cascaded blocks with five stages of radix-4 and one stage of radix-2. Since each stage requires rounding of the resulting bits while maintaining the proper S/N ratio, the convergent block floating point (CBFP) algorithm is used for the effective internal bit rounding and their method contributed to a single chip design of digital audio broadcasting system.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.1
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• pp.77-82
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• 2004

In this paper we present a barcode reader to decode two-dimensional symbology PDF417 and propose a novel method to extract the bar-space Patterns directly from the gray-level barcode image, which employs the location and the distance between extreme points of each row or column of the barcode image. This algerian proves to be very robust from the high convolutional distortion environments such as defocussing and warping, even under badly illuminating condition. If the scanned barcode image is a result of the convolution of a Gaussian-shaped point spread function with a hi-level image, popular image segmentation methods such as image thresholding can not distinguish between very narrow bar-space patterns. The Proposed algorithm shows improved Performance over current barcode readers.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.3
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• pp.8-16
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• 1999

This paper describes a VLSI design of Reed-Solomon(RS) decoder using the modified Euclid algorithm, with the main theme focused on the $\textit{GF}(2^8)$. To get area-efficient design, a number of new architectures have been devised with maximal register and Euclidean ALU unit sharing. One ALU is shared to replace 18 ALUs which computes an error locator polynomial and an error evaluation polynomial. Also, 18 registers are shared to replace 24 registers which stores coefficients of those polynomials. The validity and efficiency of the proposed architecture have been verified by simulation and by FLEX$^TM$ FPGA implementation in hardware description language VHDL. The proposed Reed-Solomon decoder, which has the capability of decoding RS(208,192,17) and RS(182,172,11) for Digital Versatile Disc(DVD), has been designed by using O.6$\mu\textrm{m}$ CMOS TLM Compass$^TM$ technology library, which contains totally 17k gates with a core area of 2.299$\times$2.284 (5.25$\textrm{mm}^2$). The chip can run at 20MHz while the DVD requirement is 3.74MHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.6
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• pp.27-33
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• 1984

This paper is an experimental gaudy on the digital hardware implementation of the R2-MF Receiver for 32 channel configurations used in signalling systems between ESS. There are many methods to detect MF signal by DSP techniques, but the requirement for MF detection needs not sharp frequency response, needs only decision about some specific frequencies exist or not at discrete frequency sampling points. The hardware used to implement this algorithm is Am 2900 series "bit-slice microprocessor" chips based on the microprogramming techniques for real time signal processing. And we used the additional Z-80A processor chips for the system control and the decision about which is the right MF signal from the detected MF spectrums. Hence we could enhance the flexibilities of the hardware and the software, this leads that this system is well suits for signalling systems used in TDM ESS.n TDM ESS.

• Spatial Information Research
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• v.19 no.3
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• pp.53-62
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• 2011

Spatial information services in indoor space are an im portant application area of GIS as in outdoor space. Unlike in outdoor space, a position in indoor space is specified by a symbolic code such as room number, rather than coordinate. Therefore tracking in indoor space is no longer a prediction of coordinates but a symbolic estimation on the current position of a moving object. In this paper, we propose a framework for tracking moving objects in indoor symbolic space with RFID sensors. First, we introduce the concepts of indoor symbolic space and tracking in indoor symbolic space, and define the accessibility graph for trackable indoor symbolic space. Second, we propose a deployment method of RFID readers and a construction algorithm of accessibility graph for trackable indoor symbolic space. Third, a tracking method is proposed for moving objects in symbolic indoor space with RFID sensors. Finally, we present an implementation exmaple and the result of experiment with real data to validate the proposed method.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.1
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• pp.102-108
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• 2010

With gradual growth of digital image contents industry connected with computer graphics technology, users require high-quality animations similar to real world and want to observe the type of fishes or their swimming types through cyber aquarium and fish encyclopedia. This study designed and developed fish growth process system to express natural and dynamic movement of fish, which is the critical in expressing submarine environment. This system proposes new mopping technique not presented in existing mopping studies as well as simulation using algorithm that newly supplemented existing fish swimming types. In addition, disease infection status is realistically expressed, which may occur depending on environmental factors during their growth process. With comprehensive fish studies, different from existing fish studies, this study examines the overall features of fish with realistic simulation.