• Title/Summary/Keyword: implementation algorithm

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A Design and Implementation of Personal Vessel Monitoring System Based on Context Aware (상황인식 기반 개인 선박 상태감시시스템 설계 및 구현)

  • Shin, Do-Sung;Lee, Seong-Ro
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.48 no.3
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    • pp.112-118
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    • 2011
  • Ship can be faced with more dangerous situations than ground vehicles due to the opened surroundings, sea. Therefore, it is very important to prevent the ship emergency by finding risk factor. In this paper, We propose context-aware monitoring system which that frequently check the condition of ship using the data that get through the installed sensor in the ship as gyro-sensor, strain-gage sensor. We analyzed sensor data through backpropagation algorithm and the Condition and Safety Information of sailing ship is transmitted to the crew's personal mobile device in the ship. Thus, moving crew can check the ship's condition in real time. As a result, we obtained about 95% accuracy for fire risk context and about 89% accuracy for body of Ship risk context in the simulated experiments.

Implementation of the Embedded System using the Laser for Measurement of Vehicle Speed and Distance (레이저를 이용한 이동차량의 속도/거리 측정용 임베디드 시스템 구현)

  • Kim, Yong-Kwon;Choe, Jin-Kyu;Ki, Jang-Geun
    • Journal of IKEEE
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    • v.8 no.1 s.14
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    • pp.108-116
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    • 2004
  • In this paper, the measurement system of speed and distance of vehicles using laser is implemented and verified through the outdoor test. The implemented system consists of a laser module and a control/speed-computation module. The Former is composed of a optics part, a transmit/receive part, and a LDC(Laser Detection and Counter), and the latter is a control part that controls the laser module and a speed computation part that calculates velocity of vehicles using a microcontroller. The algorithm to compute speed has been developed to consider characteristics of laser and surrounding conditions. The implemented system has been tested and verified on the high way, and the result shows stability of the system and accuracy of the algorithm.

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Performance Evaluation of a Time-domain Gauss-Newton Full-waveform Inversion Method (시간영역 Gauss-Newton 전체파형 역해석 기법의 성능평가)

  • Kang, Jun Won;Pakravan, Alireza
    • Journal of the Computational Structural Engineering Institute of Korea
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    • v.26 no.4
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    • pp.223-231
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    • 2013
  • This paper presents a time-domain Gauss-Newton full-waveform inversion method for the material profile reconstruction in heterogeneous semi-infinite solid media. To implement the inverse problem in a finite computational domain, perfectly-matchedlayers( PMLs) are introduced as wave-absorbing boundaries within which the domain's wave velocity profile is to be reconstructed. The inverse problem is formulated in a partial-differential-equations(PDE)-constrained optimization framework, where a least-squares misfit between measured and calculated surface responses is minimized under the constraint of PML-endowed wave equations. A Gauss-Newton-Krylov optimization algorithm is utilized to iteratively update the unknown wave velocity profile with the aid of a specialized regularization scheme. Through a series of one-dimensional examples, the solution of the Gauss-Newton inversion was close enough to the target profile, and showed superior convergence behavior with reduced wall-clock time of implementation compared to a conventional inversion using Fletcher-Reeves optimization algorithm.

Error Correction Scheme in Location-based AR System Using Smartphone (스마트폰을 이용한 위치정보기반 AR 시스템에서의 부정합 현상 최소화를 위한 기법)

  • Lee, Ju-Yong;Kwon, Jun-Sik
    • Journal of Digital Contents Society
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    • v.16 no.2
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    • pp.179-187
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    • 2015
  • Spread of smartphone creates various contents. Among many contents, AR application using Location Based Service(LBS) is needed widely. In this paper, we propose error correction algorithm for location-based Augmented Reality(AR) system using computer vision technology in android environment. This method that detects the early features with SURF(Speeded Up Robust Features) algorithm to minimize the mismatch and to reduce the operations, and tracks the detected, and applies it in mobile environment. We use the GPS data to retrieve the location information, and use the gyro sensor and G-sensor to get the pose estimation and direction information. However, the cumulative errors of location information cause the mismatch that and an object is not fixed, and we can not accept it the complete AR technology. Because AR needs many operations, implementation in mobile environment has many difficulties. The proposed approach minimizes the performance degradation in mobile environments, and are relatively simple to implement, and a variety of existing systems can be useful in a mobile environment.

GPU-ACCELERATED SPECKLE MASKING RECONSTRUCTION ALGORITHM FOR HIGH-RESOLUTION SOLAR IMAGES

  • Zheng, Yanfang;Li, Xuebao;Tian, Huifeng;Zhang, Qiliang;Su, Chong;Shi, Lingyi;Zhou, Ta
    • Journal of The Korean Astronomical Society
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    • v.51 no.3
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    • pp.65-71
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    • 2018
  • The near real-time speckle masking reconstruction technique has been developed to accelerate the processing of solar images to achieve high resolutions for ground-based solar telescopes. However, the reconstruction of solar subimages in such a speckle reconstruction is very time-consuming. We design and implement a new parallel speckle masking reconstruction algorithm based on the Compute Unified Device Architecture (CUDA) on General Purpose Graphics Processing Units (GPGPU). Tests are performed to validate the correctness of our program on NVIDIA GPGPU. Details of several parallel reconstruction steps are presented, and the parallel implementation between various modules shows a significant speed increase compared to the previous serial implementations. In addition, we present a comparison of runtimes across serial programs, the OpenMP-based method, and the new parallel method. The new parallel method shows a clear advantage for large scale data processing, and a speedup of around 9 to 10 is achieved in reconstructing one solar subimage of $256{\times}256pixels$. The speedup performance of the new parallel method exceeds that of OpenMP-based method overall. We conclude that the new parallel method would be of value, and contribute to real-time reconstruction of an entire solar image.

Design and Implementation of HomePNA 2.0 MAC Controller Circuit (HomePNA 2.0 MAC Controller 회로의 설계 및 구현)

  • Kim, Jong-Won;Kim, Dae-Young
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.1A
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    • pp.1-10
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    • 2006
  • The Home Phoneline Networking Alliance(HomePNA) 2.0 technology can establish a home network using existing in-home phone lines, which provides a channel rate of 4-32 Mbps. HomePNA 2.0 Medium Access Control(MAC) protocol adopts an IEEE 802.3 Carrier Sense Multiple Access with Collision Detection(CSMA/CD) access method, Quality of Service(QoS) algorithm, and Distributed Fair Priority Queuing(DFPQ) collision resolution algorithm. In this paper, we describe some performance analysis results of HomePNA 2.0 MAC protocol and the requirements of HomePNA 2.0 MAC controller. Then, we propose the architecture of HomePNA 2.0 MAC controller circuit, show the simulation result of each block included in HomePNA 2.0 MAC controller, and present the HomePNA 2.0 transceiver chip that we have implemented.

An Image Compression Algorithm Using the WDCT (Warped Discrete Cosine Transform) (WDCT(Warped Discrete Cosine Transform)를 이용한 영상 압축 알고리듬)

    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.24 no.12B
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    • pp.2407-2414
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    • 1999
  • This paper introduces the concept of warped discrete cosine transform (WDCT) and an image compression algorithm based on the WDCT. The proposed WDCT is a cascade connection of a conventional DCT and all-pass filters whose parameters can be adjusted to provide frequency warping. In the proposed image compression scheme, the frequency response of the all-pass filter is controlled by a set of parameters with each parameter for a specified frequency range. For each image block, the best parameter is chosen from the set and is sent to the decoder as a side information along with the result of corresponding WDCT computation. For actual implementation, the combination of the all-pass IIR filters and the DCT can be viewed as a cascade of a warping matrix and the DCT matrix, or as a filter bank which is obtained by warping the frequency response of the DCT filter bank. Hence, the WDCT can be implemented by a single matrix computation like the DCT. The WDCT based compression, outperforms the DCT based compression, for high bit rate applications and for images with high frequency components.

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Design and Implementation of Mobile CRM Utilizing Big Data Analysis Techniques (빅데이터 분석 기법을 활용한 모바일 CRM 설계 및 구현)

  • Kim, Young-Il;Yang, Seung-Su;Lee, Sang-Soon;Park, Seok-Cheon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.6
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    • pp.289-294
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    • 2014
  • In the recent enterprises and are utilizing the CRM using data mining techniques and new marketing plan. However, data mining techniques are necessary expertise, general public access is difficult, it will be subject to constraints of time and space. in this paper, in order to solve this problem, we have proposed a Mobile CRM applying the data mining method. Thus, to analyze the structure of an existing CRM system, and defines the data flow and format. Also, define the process of the system, was designed sales trend analysis algorithm and customer sales recommendation algorithm using data mining techniques. Evaluation of the proposed system, through the test scenario to ensure proper operation, it was carried out the comparison and verification with the existing system. Results of the test, the value of existing programs and data matches to verify the reliability and use queries the proposed statistical tables to reduce the analysis time of data, it was verified rapidity.

Implementation of Memory controller for Punctuality Guarantee from Memory-Free Inspection Equipment using DDR2 SDRAM (DDR2 SDRAM을 이용한 비메모리 검사장비에서 정시성을 보장하기 위한 메모리 컨트롤러 구현)

  • Jeon, Min-Ho;Shin, Hyun-Jun;Kang, Chul-Gyu;Oh, Chang-Heon
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.05a
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    • pp.136-139
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    • 2011
  • The conventional semiconductor equipment has adopted SRAM module as the test pattern memory, which has a simple design and does not require refreshing. However, SRAM has its disadvantages as it takes up more space as its capacity becomes larger, making it difficult to meet the requirements of large memories and compact size. if DRAM is adopted as the semiconductor inspection equipment, it takes up less space and costs less than SRAM. However, DRAM is also disadvantageous because it requires the memory cell refresh, which is not suitable for the semiconductor examination equipments that require correct timing. Therefore, In this paper, we will proposed an algorithm for punctuality guarantee of memory-free inspection equipment using DDR2 SDRAM. And we will produced memory controller using punctuality guarantee algorithm.

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A design of LDPC decoder supporting multiple block lengths and code rates of IEEE 802.11n (다중 블록길이와 부호율을 지원하는 IEEE 802.11n용 LDPC 복호기 설계)

  • Kim, Eun-Suk;Park, Hae-Won;Na, Young-Heon;Shin, Kyung-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2011.05a
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    • pp.132-135
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    • 2011
  • This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

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