• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.3
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• pp.11-22
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• 2010

This paper is a study on implementation of intelligent image surveillance system using context information and supplements temporal-spatial constraint, the weak point in which it is hard to process it in real time. In this paper, we propose scene analysis algorithm which can be processed in real time in various environments at low resolution video(320*240) comprised of 30 frames per second. The proposed algorithm gets rid of background and meaningless frame among continuous frames. And, this paper uses wavelet transform and edge histogram to detect shot boundary. Next, representative key-frame in shot boundary is selected by key-frame selection parameter and edge histogram, mathematical morphology are used to detect only motion region. We define each four basic contexts in accordance with angles of feature points by applying vertical and horizontal ratio for the motion region of detected object. These are standing, laying, seating and walking. Finally, we carry out scene analysis by defining simple context model composed with general context and emergency context through estimating each context's connection status and configure a system in order to check real time processing possibility. The proposed system shows the performance of 92.5% in terms of recognition rate for a video of low resolution and processing speed is 0.74 second in average per frame, so that we can check real time processing is possible.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.47 no.6
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• pp.1-7
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• 2010

This paper presents a novel implementation on multimedia fingerprinting algorithm based on BCH (Bose-Chaudhuri-Hocquenghem) code. The evaluation is put in force the colluder detection to n-1. In the proposed algorit hm, the used collusion attacks adopt logical combinations (AND, OR and XOR) and average computing (Averaging). The fingerprinting code is generated as below step: 1. BIBD {7,4,1} code is generated with incidence matrix. 2. A new encoding method namely combines BIBD code with BCH code, these 2 kind codes are to be fingerprinting code by BCH encoding process. 3. The generated code in step 2, which would be fingerprinting code, that characteristic is similar BCH {15,7} code. 4. With the fingerprinting code in step 3, the collusion codebook is constructed for the colluder detection. Through an experiment, it confirmed that the ratio of colluder detection is 86.6% for AND collusion, 32.8% for OR collusion, 0% for XOR collusion and 66.4% for Averaging collusion respectively. And also, XOR collusion could not detect entirely colluder and on the other hand, AND and Averaging collusion could detect n-1 colluders and OR collusion could detect k colluders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1263-1270
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• 2004

A low-power 64-point FFT/IFFT processor core is designed, which is an essential block in OFDM-based wireless LAM modems. The radix-2/418 DIF (Decimation-ln-Frequency) FFT algorithm is implemented using R2SDF (Radix-2 Single-path Delay Feedback) structure. Some design techniques for low-power implementation are considered from algorithm level to circuit level. Based on the analysis on infernal data flow, some unnecessary switching activities have been eliminated to minimize power dissipation. In circuit level, constant multipliers and complex-number multiplier in data-path are designed using truncation structure to reduce gate counts and power dissipation. The 64-point FFT/IFFT core designed in Verilog-HDL has about 28,100 gates, and timing simulation results using gate-level netlist with extracted SDF data show that it can safely operate up to 50-MHz＠2.5-V, resulting that a 64-point FFT/IFFT can be computed every 1.3-${\mu}\textrm{s}$. The functionality of the core was fully verified by FPGA implementation using various test vectors. The average SQNR of over 50-dB is achieved, and the average power consumption is about 69.3-mW with 50-MHz＠2.5-V.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.2
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• pp.32-45
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• 2000

This paper presents the analytic derivation of the SINR, when a linear array antenna is accommodated into the cellular CDMA basestation receiver, in relation to the two major performance effecting factors in beamforming(BF) applications, i. e., the direction selectivity, which refers to the narrowness of the mainbeam width, and the direction-of-arrival(DOA) estimation accuracy. The analytically derived results are compared with the operation simulation of the receiver realized with the several BF algorithms and their agreements are confirmed, consequently verifying the correctness of the analysis and the operation simulation. In order to investigate separately the effects of the errors occurring in the direction estimation and in the interference suppression, which are the two major functional components of general BF algorithms, both the algorithms of steering BF and the minimum- variance- distortionless-response(MVDR) BF are applied to the analysis. A signal model to reflect the spatially scattering phenomenon of the RF waves entering into the .:nay antenna, which directly affects on the accuracy of the BF algorithm's direction estimation, is also suggested in this paper and applied to the analysis and the operation simulation. It is confirmed from the results that the enhancement of the direction selectivity of the away antenna is not desirable in view of both the implementation economy and the BF algorithm's robustness to the erroneous factors. Such a trade-off characteristics is significant in the sense that it can be capitalized to obtain an economic means of BF implementation that does not severely deteriorate its performance while ensuring the robustness to the erroneous effects, consequently manifesting the significance of the analysis results of this paper that can be used as a design reference in developing BF algorithms to the cellular CDMA system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.3
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• pp.461-467
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• 2003

This paper proposes the method of mobility implementation for location searching in the intelligence wireless ATM networks that expand and apply standard broadband signaling capabilities, and analyze the performance based on the numerical algorithm. The existing B-ISDN UNI protocol stack demands the location search mechanism to determine the location of mobile terminal in the wireless ATM networks because it use single protocol through the fixed PTP interface or PTM interface that don't support terminal mobility. The proposed method make possible the dynamic mobility at a part of wireless access by minimizing the signaling load without a falling-off in system performance by using the intelligence network technology according to the expansion of ATM and B-ISDN signaling integration based on the fixed networks. We implemented the performance analysis by MFC modeling based on numerical algorithm, and realized the efficiency of expenses by carrying out the comparative signaling performance evaluation to measure the relative gains of location search service in the intelligence wireless ATM system. The obtained results have the flexibility to operate in the public B-ISDN network environment without a change of existing B-ISDN/ATM NNI signaling reference to support the wireless ATM access system, and can easily expand to correspond to terminal mobility and various multimedia services in the next broadband PCS.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2000.05a
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• pp.465-469
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer (PADFE) using a 0.25-${\mu}{\textrm}{m}$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stage are inserted into the critical path of the ADFE by using delayed least-mean-square (DLMS) algorithm Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The singl-chip PADFE contains about 205,000 transistors on an area of about 1.96$\times$1.35-$\textrm{mm}^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.3
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• pp.31-38
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• 2005

This paper proposes an implementation method of intelligent characters that can properly adapt to action patterns of opponent characters in fighting games by using genetic algorithm. For this intelligent characters, past actions patterns of opponent characters should be included in the learning process. To verify the effectiveness of the proposed method, two types of experiments are performed and their results are compared. In first experiment(exp-1), intelligent characters consider current action and its step of an opponent character. In second experiment (exp-2), on the other hands, they take past actions of an opponent characters into account additionally. As a performance index, the ratio of score obtained by an intelligent character to that of an opponent character is adopted. Experimental results shows that even if the performance index of exp-1 is better than that of exp-2 at the beginning of stages, but the performance index of exp-2 outperforms that of exp-1 as stages go on. Moreover, optimum solutions are always found in all experimental cases in exp-2. Futhermore, intelligent characters in exp-2 could learn moving actions (forward and backward) and waiting actions for getting more scores through self evolution.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.