• 전자공학회논문지 IE
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• v.45 no.4
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• pp.27-32
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• 2008

This paper presents the implementation of simple genetic algorithm using hardware description language for evolvable hardware embedded system. Evolvable hardware refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. So, it is especially suited to applications where no hardware specifications can be given in advance. Evolvable hardware is based on the idea of combining reconfigurable hardware device with evolutionary computation, such as genetic algorithm. Because of parallel, no function call overhead and pipelining, a hardware genetic algorithm give speedup over a software genetic algorithm. This paper suggests the hardware genetic algorithm for evolvable embedded system chip. That includes simulation results for several fitness functions.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.186-189
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• 2003

This paper discussed whole concept of bluetooth baseband and studied its detail algorithm. Important blocks, access code, security and clock management, are implemented and verified to hardware and firmware according to Specification ver.1.1. Then implementation results are compared and examined. Finally, this paper suggested the efficient system implementation method. By using test board, it could confirm that suggested implementation communicated smoothly.

• Proceedings of the IEEK Conference
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• 2002.06d
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• pp.171-174
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• 2002

This paper presents an implementation method of phasor measurement device, which is based on the FPGA implementation of the sliding-DFT The design is verified by the timing simulation of its operation. The error effect of coefficient approximation and frequency deviation in the recursive implementation of the sliding-DFT is analytically derived and verified with the computer simulations.

• The Journal of Society for e-Business Studies
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• v.8 no.1
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• pp.113-119
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• 2003

This paper proposes a new multiplicative inverse algorithm for the Galois field GF (2/sup m/) whose elements are represented by optimal normal basis type Ⅱ. One advantage of the normal basis is that the squaring of an element is computed by a cyclic shift of the binary representation. A normal basis element is always possible to rewrite canonical basis form. The proposed algorithm combines normal basis and canonical basis. The new algorithm is more suitable for implementation than conventional algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1394-1402
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• 1997

In this work, an efficient test algorithm and BIST architeture a for embedded memories are presented. The proposed test algorithm can fully detect stuck-at fault, transition fault, coupling fault. Moreover, the proposed test algorithm can detect nighborhood pattern sensitive fault which could not be detected in previous march test algoarithms. The proposed test algorithm perposed test algorithm performs testing for neghborhood pattern sensitive fault using backgroung data which has been used word-oriented memory testing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.1
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• pp.57-67
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• 2005

Fast scalar multiplication of points on elliptic curve is important for elliptic curve cryptography applications. In order to vary field sizes depending on security situations, the cryptography coprocessors should support variable length finite field arithmetic units. To determine the effective variable length finite field arithmetic architecture, two well-known curve scalar multiplication algorithms were implemented on FPGA. The affine coordinates algorithm must use a hardware division unit, but the projective coordinates algorithm only uses a fast multiplication unit. The former algorithm needs the division hardware. The latter only requires a multiplication hardware, but it need more space to store intermediate results. To make the division unit versatile, we need to add a feedback signal line at every bit position. We proposed a method to mitigate this problem. For multiplication in projective coordinates implementation, we use a widely used digit serial multiplication hardware, which is simpler to be made versatile. We experimented with our implemented ECC coprocessors using variable length finite field arithmetic unit which has the maximum field size 256. On the clock speed 40 MHz, the scalar multiplication time is 6.0 msec for affine implementation while it is 1.15 msec for projective implementation. As a result of the study, we found that the projective coordinates algorithm which does not use the division hardware was faster than the affine coordinate algorithm. In addition, the memory implementation effectiveness relative to logic implementation will have a large influence on the implementation space requirements of the two algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.9
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• pp.1702-1708
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• 2007

Dragon Stream Cipher is proposed for software base implementation in the eSTREAM project. Now this stream cipher is selected as a phase 3 focus candidate. Dragon is a new stream cipher contructed using a single word based NIFSR(non-linear feed back shift register) and 128/256 key/IV(Initialization Vector). Dragon is the keystream generator that produce 64bits of keystream. In this paper, we present an implementation of Drag(m stream cipher algorithm in hardware. Finally, the implementation is on Altera FPGA device, EP3C35F672I and the timing simulation is done on Altera's Quartus II. A result of 111MHz maximum clock rate and 7.1Gbps is throughput is obtained from the implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.34 no.1
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• pp.11-19
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• 2024

The increased utilization of the FFT in signal processing, cryptography, and various other fields has highlighted the importance of optimization. In this paper, we propose the implementation of an accelerator that processes the radix-2 16 points FFT algorithm more rapidly and efficiently than FFT implementation of existing studies, using FPGA(Field Programmable Gate Array) hardware. Leveraging the hardware advantages of FPGA, such as parallel processing and pipelining, we design and implement the FFT logic in the PL (Programmable Logic) part using the Verilog language. We implement the FFT using only the Zynq processor in the PS (Processing System) part, and compare the computation times of the implementation in the PL and PS part. Additionally, we demonstrate the efficiency of our implementation in terms of computation time and resource usage, in comparison with related works.

• Journal of KIISE:Information Networking
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• v.32 no.2
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• pp.254-260
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• 2005

In the guaranteed service, a real-time scheduling algorithm must achieve both high level of network utilization and scalable implementation. Here, network utilization indicates the number of admitted real-time sessions. Unfortunately, existing scheduling algorithms either are lack of scalable implementation or can achieve low network utilization. For example, scheduling algorithms based on time-stamps have the problem of O(log N) scheduling complexity where N is the number of sessions. On the contrary, round-robin algorithms require O(1) complexity. but can achieve just a low level of network utilization. In this paper, we propose a scheduling algorithm that can achieve high network utilization without losing scalability. The proposed algorithm is a Hierarchical Round-Robin (H-RR) algorithm that utilizes multiple rounds with different interval sizes. It provides latency bounds similar to those by Packet-by-Packet Generalized Processor Sharing (PGPS) algorithm using a sorted-Priority queue. However, H-RR requires a constant time for implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.12
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• pp.1624-1630
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• 2019

With the increase in there are smart devices penetration around the world, services related to exercise checks are attracting attention. However, there is existing exercise amount measurement service does not use the altitude information, or because the use of an algorithm that does not corrected the GPS altitude error is not accurate movement distance provided have a problem. Therefore, in this paper, to improve the existing problems, Kalman-filter-based user movement distance measurement algorithm is designed and implementation of improved by using the Kalman-filter based GPS and barometric altimeter sensor fusion algorithm to improve the altitude value the accuracy and of calculate the coordinate plane distance. As a result of comparing the designed and implementation of algorithm with the existing algorithms, it is confirmed that the proposed algorithm improves the accuracy by about 2.17%.