• 전기전자학회논문지
• /
• 제4권2호
• /
• pp.266-273
• /
• 2000

OCXO (Oven Controlled X-tal Oscillator)의 주파수 모델이 holdover 알고리즘을 DP-PLL (Digital Processing-Phase Locked Loop) 시스템에 적용하기 위해 제안되었다. 이 모델은 온도와 OCXO의 노화에 따라 2차 다항식으로 간단하게 표현된다. 모델 변수들은 LSM (Least Squared Method)을 적용한 실험 데이터로부터 얻어진다. holdover 알고리즘은 다른 실험 데이터를 사용한 동일한 모델로 모의실험 할 수 있다.

• 제어로봇시스템학회논문지
• /
• 제21권7호
• /
• pp.669-676
• /
• 2015

In this paper, we described the simulation results of the phase offset performance of a clock in holdover mode which was normally operated in GPS Disciplined Oscillator (GPSDO). In the TIE model, we included the time error term caused by environmental temperature variation because one of the most important parameters of clock phase error is the frequency offset and drift caused by the variation of temperature. For the simulation, we employed Maximum Time Interval Error (MTIE) for the performance evaluation when the frequency offset and drift are estimated by using an Unbiased Finite Impulse Response (UFIR) filter with ladder algorithm. We assumed that the noise in the GPS measurement is white Gaussian with zero mean and 1 ns standard deviation, and temperature linearly varies with a slope of $1{^{\circ}C}$ per hour. From the simulation results, the followings were observed. First, with the estimation error of temperature of less than 3 % and the temperature compensation period of less than 900 seconds, the requirement of CDMA2000 phase synchronization under 10 us could be achieved for more than 40,000 seconds holdover time if we employ an OCXO (Oven Controlled Crystal Oscillator) clock. Second, in order to achieve the requirement of LTE-TDD under 1.5 us for more than 10,000 seconds holdover time, below 3 % estimation error and 500 seconds should be retained if a Rubidium clock is adopted.

• Journal of Positioning, Navigation, and Timing
• /
• 제5권3호
• /
• pp.157-163
• /
• 2016

Clocks for time synchronization using radio signals such as global navigation satellite system (GNSS) may lose reference signals by intentional or unintentional jamming. This is called as holdover. When holdover occurs, a clock goes into free run in which synchronization performance is degraded considerably. In order to maintain the required precise time synchronization during holdover, accurate estimation on main parameters such as frequency offset and frequency drift is needed. It is necessary to implement an optimum filter through various simulation tests by creating clock noise in accordance with given specifications in order to estimate the main parameters accurately. In this paper, a method that creates clock noise in accordance with given specifications is described.

• 한국전자파학회:학술대회논문집
• /
• 한국전자파학회 2005년도 종합학술발표회 논문집 Vol.15 No.1
• /
• pp.107-110
• /
• 2005

This paper describes the design and fabrication of synchronous clock recovery module for S-DMB Gap Filler. Using the 2.304MHz TTL signal from gap filler tuner, clock recovery module with 10MHz output frequency including holdover function is designed. The measured performance of the clock recovery module shows a stability of less than 0.01ppm, 29 sec stability time, 10 sec holdover time, and maximum -113dBc/Hz@100Hz phase noise.

• 한국통신학회논문지
• /
• 제31권10A호
• /
• pp.1003-1013
• /
• 2006

IEEE802.11g VoWLAN (Voice over Wireless LAN) 단말기는 802.11b 전용 단말기에 비해 통화시간이 30 % 이상 감소하는 문제점이 있어 통화시간이 문제로 대두되고 있다. 일반적으로, 802.11g에서는 멀티캐리어 방식인 OFDM (Orthogonal Frequency Division Multiplexing) 변조방식을 사용하여 54 Mbps속도로 전송하기 때문에 기존의 802.11b MAC (Medium Access Control) 전송방식과 비교하여 통화시간을 만족시키는 것이 어렵다. 본 논문에서는 802.11g 규격을 적용한 단말기에서 통화중 Power Save 방법으로 Holdover Time을 처음으로 제안하므로 통화시간을 만족시킨다. 다만, 통화 단말기 수 증가에 따른 네트워크 혼잡으로 경합 창 (contention window)이 많이 발생하여, Back-off 수 증가로 인한 통화품질(QoS)의 문제가 발생하지만, QoS 해결 방안으로 다운 링크 시 802.11 G.711 Sequence Number를 단말기 MAC 단에서 분석하여 손실율에 따른 Holdover Time을 가변 하는 방법을 제안하므로 이 문제를 해결한다. 802.11b/g 소비전류 분석과 통화 단말기 증가에 따른 네트워크 혼잡에 의한 MAC 파라미터 성능을 분석하며, VQT장비와AiroPeek를 이용하여 실제적인 데이터를 분석한다.

• 항공우주시스템공학회지
• /
• 제7권3호
• /
• pp.51-57
• /
• 2013

This study describes the Federal Aviation Administration(FAA) certification policy for approving the use of Type II, III, and IV deicing/anti-icing fluids on small category airplanes. These fluids can be characterized as non-Newtonian, pseudo-plastic fluids, also known as "thickened" fluids. Deicing fluids are used before takeoff to remove frost or ice contamination, while anti-icing fluids are used before takeoff to prevent frost or ice contamination from occurring for a period of time(referred to as "holdover time") after application. Thickened deicing/anti-icing fluids can affect airplane performance and handling characteristics and their residue may cause stiff or frozen flight controls. This study also describes an approval process that may be used by type certificate holders and applicants for a type certificate under parts 23 to support operational use of these fluids on their airplanes.

• Journal of Positioning, Navigation, and Timing
• /
• 제13권1호
• /
• pp.111-115
• /
• 2024

This study builds a machine learning model optimized for clocks among various techniques in the field of artificial intelligence and applies it to clock stabilization or synchronization technology based on atomic clock noise characteristics. In addition, the possibility of providing stable source clock data is confirmed through the characteristics of machine learning predicted values during holdover of atomic clocks. The proposed machine learning model is evaluated by comparing its performance with the AutoRegressive Integrated Moving Average (ARIMA) model, an existing statistical clock prediction model. From the results of the analysis, the prediction model proposed in this study (MSE: 9.47476) has a lower MSE value than the ARIMA model (MSE: 221.2622), which means that it provides more accurate predictions. The prediction accuracy is based on understanding the complex nature of data that changes over time and how well the model reflects this. The application of a machine learning prediction model can be seen as a way to overcome the limitations of the statistical-based ARIMA model in time series prediction and achieve improved prediction performance.

• 한국ITS학회:학술대회논문집
• /
• 한국ITS학회 2006년도 제5회 추계학술대회 및 정기총회
• /
• pp.108-112
• /
• 2006

• 한국실내디자인학회:학술대회논문집
• /
• 한국실내디자인학회 2007년도 춘계학술대회 논문집
• /
• pp.75-76
• /
• 2007

Recently with increasing interest in the natural science history education, a lot of natural science museums have been developed in various locations. This project is located in one of the biggest Paleozoic site, Taebak Kangwon-do. This kind museum has had important rolls in terms of education for student, destination for traveling and reservation of important holdover of the old ages. To do those kind of parts, this project has been designed with concepts and themes like; i. being organized with story telling structure with theme "secret of life and earth from Taebak" ii. combining experiences between outdoor experimental search for the real fossils and indoor educational interactions with real size model and moving films. iii. designing with strong identities of Paleozoic era. For the design identities the outer appearance was designed with motive of trilbites in an abstract way and inside was finished with exposed concrete and various size of moving films projected to walls and floor to emphasize real scale experience of the old ages.

• Journal of Communications and Networks
• /
• 제7권1호
• /
• pp.1-12
• /
• 2005

Ethernet is being deployed in metropolitan area networks (MANs) as a lower-cost alternative to SONET-based infrastructures. MANs are usually required to support common communication services, such as voice and frame relay, based on legacy synchronous TDM technology in addition to asynchronous packet data transport. This paper addresses the clock synchronization problem that arises when transporting synchronous services over an asynchronous packet infrastructure, such as Ethernet. A novel algorithm for clock synchronization is presented combining time-stamp methods used in the network time protocol (NTP) with signal processing techniques applied to measured packet interarrival times. The algorithm achieves the frequency accuracy, stability, low drift, holdover performance, and rapid convergence required for viable emulation of TDM circuit services over Ethernet.