• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.28-33
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• 2020

Plasma etching process employs high density plasma to create surface chemistry and physical reactions, by which to remove material. Plasma chamber includes silicon-based materials such as a focus ring and gas distribution plate. Focus ring needs to be replaced after a short period. For this reason, there is a need to find materials resistant to erosion by plasma. The developed chemical vapor deposition processing to produce silicon carbide parts with high purity has also supported its widespread use in the plasma etch process. Silicon carbide maintains mechanical strength at high temperature, it have been use to chamber parts for plasma. Recently, besides the structural aspects of silicon carbide, its electrical conductivity and possibly its enhanced life time under high density plasma with less generation of contamination particles are drawing attention for use in applications such as upper electrode or focus rings, which have been made of silicon for a long time. However, especially for high purity silicon carbide focus ring, which has usually been made by the chemical vapor deposition method, there has been no study about quality improvement. The goal of this study is to reduce surface roughness and depth of damage by diamond tool grit size and tool dressing of diamond tools for precise dimensional assurance of focus rings.

• Journal of the Semiconductor & Display Technology
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• v.21 no.3
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• pp.39-44
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• 2022

The light extraction technology for improving the light efficiency of OLEDs is the core technology for extracting the light inside the OLEDs to the outside. This study demonstrates a simple method to generate random nanostructures (RNSs) containing high refractive index nanoparticles to improve light extraction and viewing angle characteristics. A simple dry low-temperature process makes the nanostructured scattering layer on the polymer resin widely used in the industry. The scattering layer has the shape of randomly distributed nanorods. To control optical properties, we focused on changing the shape and density of RNSs and adjusting the concentration of high refractive index nanoparticles. As a result, the film of the present invention exhibits a perpendicular transmittance of 85% at a wavelength of 550 nm. This film was used as a scattering layer to reduce substrate mode loss and improve EL efficiency in OLEDs.

• Current Optics and Photonics
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• v.3 no.6
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• pp.583-589
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• 2019

We report experimental results on 940-nm 350-mW AlGaAs/InGaAs transverse single-mode laser diodes (LDs) adopting graded-index separate confinement heterostructures (GRIN-SCH) and p,n-clad asymmetric structures, with improved temperature and small-divergence beam characteristics under high-output-power operation, for a three-dimensional (3D) motion-recognition sensor. The GRIN-SCH design provides good carrier confinement and prevents current leakage by adding a grading layer between cladding and waveguide layers. The asymmetric design, which differs in refractive-index distribution of p-n cladding layers, reduces the divergence angle at high-power operation and widens the transverse mode distribution to decrease the power density around emission facets. At an optical power of 350 mW under continuous-wave (CW) operation, Gaussian narrow far-field patterns (FFP) are measured with the full width at half maximum vertical divergence angle to be 18 degrees. A threshold current (I_th) of 65 mA, slope efficiency (SE) of 0.98 mW/mA, and operating current (I_op) of 400 mA are obtained at room temperature. Also, we could achieve catastrophic optical damage (COD) of 850 mW and long-term reliability of 60℃ with a TO-56 package.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.376-376
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• 2012

Semiconductor nanowires (NWs) are future building block for nano-scale devices. Especially, Ge NWs are fascinated material due to the high electrical conductivity with high carrier mobility. It is strong candidate material for post-CMOS technology. However, thermal stability of Ge NWs are poor than conventional semiconductor material such as Si. Especially, when it reduced size as small as nano-scale it will be melted around CMOS process temperature due to the melting point depression. Recently, Graphene have been intensively interested since it has high carrier mobility with single atomic thickness. In addition, it is chemically very stable due to the $sp^2$ hybridization. Graphene films shows good protecting layer for oxidation resistance and corrosion resistance of metal surface using its chemical properties. Recently, we successfully demonstrated CVD growth of monolayer graphene using Ge catalyst. Using our growth method, we synthesized Ge/graphene core/shell (Ge@G) NW and conducted it for highly thermal stability required devices. We confirm the existence of graphene shell and morphology of NWs using SEM, TEM and Raman spectra. SEM and TEM images clearly show very thin graphene shell. We annealed NWs in vacuum at high temperature. Our results indicated that surface melting phenomena of Ge NWs due to the high surface energy from curvature of NWs start around $550^{\circ}C$ which is $270^{\circ}C$ lower than bulk melting point. When we increases annealing temperature, tip of Ge NWs start to make sphere shape in order to reduce its surface energy. On the contrary, Ge@G NWs prevent surface melting of Ge NWs and no Ge spheres generated. Furthermore, we fabricated filed emission devices using pure Ge NWs and Ge@G NWs. Compare with pure Ge NWs, graphene protected Ge NWs show enhancement of reliability. This growth approach serves a thermal stability enhancement of semiconductor NWs.

• Proceedings of the KIPE Conference
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• 2012.07a
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• pp.343-344
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• 2012

In high power PV generation system, the solar cell normally generates wide output voltage depending on the insolation, cell's temperature and shade effect. This paper will propose a high efficiency converter allowing the wide input voltage to supply stable voltage with the controller and operation for the PV generation system. The proposed converter consists of two stages comprising SEPIC with a coupled inductor and LLC, which generates 24 V of output at the final output terminal. In this paper, a design method and experimental results with a test-bed of 50 W will be presented to validate the proposed converter.

• Journal of the Semiconductor & Display Technology
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• v.14 no.2
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• pp.61-65
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• 2015

SiC composite materials are usually used to very high temperature condition such as thermal protection system materials at space vehicles, combustion chambers or engine nozzles because they have high specific strength and good thermal properties at high temperature. One of the most widely used fabrication methods of SiC composites is the chemical vapor infiltration (CVI) process. During the process, chemical gases including Si are introduced into porous preform which is made by carbon fibers for infiltration. Since the processes take a very long time, it is important to reduce the process time in designing the reactors and processes. In this study, both the gas flow and heat transfer in the reactors during the processes are analyzed using a computational fluid dynamics method in order to design reactors and processes for uniform, high quality SiC composites. Effects of flow rate and heater temperature as process parameters to the infiltration process were examined.

• ETRI Journal
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• v.39 no.6
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• Journal of the Semiconductor & Display Technology
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• v.22 no.1
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• pp.83-87
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• 2023

Y₂SiO₅ Powder based on silicon and yttrium is well known as powder phosphors due to their excellent sustainability and efficiency. A new electroluminescence device was fabricated with Y₂SiO₅:Eu³⁺ powder phosphors though a simple screen printing method. The powder-dispersed electroluminescence device consisted of the Y₂SiO₅:Eu³⁺ powder-dispersed phosphor layer and BaTiO₃-dispersed dielectric layer. The annealing temperature of the phosphor for the best powder electroluminescence performance was optimized to high temperature in ambient atmosphere though a solid-state reaction. The Eu³⁺ concentration for the best device performance was also investigated and furthermore, the thermal dependence of the electroluminescence intensity was investigated at the operating voltage at 100℃, which is the Curie temperature of the BaTiO₃ layer. And the intensity was exponentially increased with voltage and increased linearly with frequency.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2006.10a
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• pp.10-13
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• 2006

This paper describes on the fabrication and characteristics of a 3C-SiC (Silicon Carbide) micro pressure sensor for harsh environment applications. The implemented micro pressure sensor used 3C-SiC thin-films heteroepitaxially grown on SOI (Si-on-insulator) structures. This sensor takes advantages of the good mechanical properties of Si as diaphragms fabricated by D-RIE technology and temperature properties of 3C-SiC piezoresistors. The fabricated pressure sensors were tasted at temperature up to $250^{\circ}C$ and indicated a sensitivity of 0.46 mV/V*bar at room temperature and 0.28 mV/V*bar at $250^{\circ}C$. The fabricated 3C-Sic/SOI pressure sensor presents a high-sensitivity and excel lent temperature stability.