• Journal of electromagnetic engineering and science
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• v.7 no.1
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• pp.1-6
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• 2007

Recently, Mc(Multi-code) modulation/demodulation(modem) technique has been explored for high speed data transmission in wireless environment. The conventional Mc modem generates some side effects such as allocating Walsh codes, which motivates to propose a novel Mc modem method with sub-code. Our proposed system should expanded the size of sub-code to provide high-rate data transmission, which also affect adversely to the performance of the system with high PAPR(Peak to Average Power Ratio). Thus, in this paper, we propose a novel pre-coded Multi-Dimensional HCOC(High Capacity Orthogonal Code) Mc modem technique to reduce the high PAPR, which enables the performance improvement. This proposed system can be easily designed by concatenating HCOC Mc modem with the generic Mc modem. The pre-coding technique that is used in this paper is CAC(Constant Amplitude Coding), that helps the system maintain the constant transmission power and reduce the maximum transmission power.

• Journal of the Semiconductor & Display Technology
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• v.9 no.2
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• pp.7-10
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• 2010

In this paper, we design a modem SoC (System on Chip) for low power consumption and high speed wireless communications. Among various schemes of high speed communications, an MB-OFDM (Multi Band-Orthogonal Frequency Division Multiplexing) UWB (Ultra-Wide-Band) chip is designed. The MB-OFDM uses wide-band frequency to provide high speed data rate. Additionally, the system imposes no interference to other services. The 90nm CMOS (Complementary Metal-Oxide Semiconductor) technology is used for the SoC design. Especially, power management mode is implemented to reduce the power consumption.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2628-2630
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• 2002

This paper describes the design and implementation of the OFDM Modem using FPGA. The proposed OFDM method is based on IEEE 802.11a high-speed wireless LAN standard. The proposed and designed Pipeline FFT processor adopt the Radix-$2^2$SDF scheme. This method has a simple architecture and highly increases the calculation speed. And also it decreases the required number of registers. Therefore the proposed OFDM Modem reduces hardware size and improves the calculation speed. The OFDM Modem is implemented using $FLEX^{TM}$ FPGA.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.4
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• pp.325-332
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• 2004

In this paper, we propose a new DSSS-QPSK baseband modem receiver structure. A general receiver consists of matched filter, do-spreader, and DLL(Delay Locked Loop). In this paper, the matched filter plays a role of the do-spreader using the structure similarities between the matched filter and the de-spreader. As a result of the new receiver architecture, we can reduce the computational expenses and get the simpler receiver structure. This result can be used as an important part in designing the high speed modem. And, through the computer simulation and the experiment with the proposed architecture, we show that the proposed receiver structure yields fast operation speed and simple overall architecture.

• Proceedings of the IEEK Conference
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• 2000.06a
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• pp.73-76
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• 2000

In tendency of digitalization, we studied about the purpose of digital modem for MRI spectrometer and advantage of digital modem compared with analog one. We introduce requirements lot designing transmitter of high speed digital modem for MRl spectrometer We also introduce its top-level and mid-level architecture. The transmitter is composed of CPC-P interface block, DUC & DAC block, RF block, master clock generation block, MCU block. Especially, DUC and its control parts are studied in detail. DUC and DAC can operate up to 52MHz and 100Msps, respectively. However we uses 35MHz as master clock and this paper shows its validity through simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.1
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• pp.84-89
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• 2007

In order to design and test an SoC modem for high speed communication, the platform with the architecture of such high speed communication is needed. That platform is needed for testing large data in speed of 500Mbps. This paper shows that transmission data can be uploaded and downloaded by 250Mbps between a virtual modem target board and a PC through the AHB-PCI IP and the speed of based on DPRAM and PCI.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.53-54
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• 2007

As Cable Network is developing for 2-way high speed data service, it should be developed to transfer high speed data using limited bandwidth. If QAM is using for this, synchronization algorithms become important system parameters. In this paper, we present two methods of coarse timing recovery using CAZAC sequence for cable modem uplink.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.2
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• pp.102-106
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• 2011

The transfer capability of HFC (Hybrid Fiber Coax) network is superior to xDSL. HFC network, however, is not suitable for transferring high quality video due to cable model interfaces. For the services of high quality IPIV or VOD, the extra exclusive downstream transfer system is required without upgrading pre-equipped cable modem and service capability. This paper is aimed to develop the extra exclusive downstream transfer system not changing existing cable modem system but providing same quality of services. This system is composed of the extra exclusive downstream IP-cable sender and modem. This sender and modem have 30 Mbps transfer capability and HDTV stream can be served in the Cable TV network using 21 Mbps HDTV transport stream.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.6
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• pp.612-620
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• 1987

In this paper, the optical modem for data link realization is designed with the advantages of optical fiber, large bandwidth, high speed and long haul communication. Modem interface, CCITT V.24 and EIA RS-232C is adopted for the compatibility with existing systems, and biphase coding format is used for digital modulation. And also, modem has serveral loopback test facility in order to diagnose system itself. Optical transmitter and receiver are designed to have the receiving sensitivity of -30dBm at $10^-9$BER in the short wavelength region. Developed system is capable of transmitting data rate at 1200bps up to 57.6Kbps in sync., and at any bps within DC to 200Kbps in async transmission.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.194-197
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• 2003

We proposed Binary ASK system for 1Giga bit Modem. The Binary ASK system has a high speed shutter transmitter and no IF receiver only by symbol synchronization. The advantage of proposed system is that circuitry is very simple without IF process. The disadvantage of proposed system are that line spectrum occurs unordinary interference to other channels, and enhancement to 4-level system is impossible due to its large SNR degradation.