• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.262-263
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• 2007

In this paper, fully embedded and miniaturized diplexer has been designed, fabricated, and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23dB at 824-894MHz and -0.7 and -22dB at 1850-1990MHz, respectively. Its size is 3.9mm$\times$3.9mm$\times$ 0.77mm (height). The fabricated diplexer is the smallest one which is fully embedded into low cost organic package substrate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.7
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• pp.713-721
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• 2004

This paper presents a high Performance LNA based on InGaP/GaAs HBT for 5.4㎓ WAM band applications. During the past days, InGaP/GaAs HBT has been being used for mainly high power amplifiers, but InCaP/GaAs is recognized as a suitable device for RF single chip. At this point, the research about a high performance LNA based on InGaP/GaAs HBT must be preceded, and in this paper, a excellent linearity and noise characteristics LNA based on InGaP/GaAs HBT is desisted and fabricated. The LNA is integrated in new of 0.9${\times}$0.9$\textrm{mm}^2$ single chip with high Q spiral inductors and MIM capacitors. The proposed LNA is biased at current point for optimum noise figure and gain characteristics, futhermore, excellent linearity is achieved. The proposed LNA shows 13㏈ gain, 2.1㏈ noise figure, and excellent linearity in terms of IIP3 of 5.5㏈m.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.71-71
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• 2009

This paper describes a simple, on-chip CMOS compatible the thin-film inductor applied for the dc-dc converters. A fully CMOS-compatible thin-film inductor with a bottom NiFe core is integrated with the DC-DC converter circuit on the same chip. By eliminating ineffective top magnetic layer, very simple process integration was achieved. Fabricated monolithic thin film inductor showed fairly high inductance of 2.2 ${\mu}H$ and Q factor of 11.2 at 5MHz. When the DC-DC converter operated at $V_{in}=3.3V$ and 5MHz frequency, it showed output voltage $V_{out}=8.0V$, and corresponding power efficiency was 85%.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2003.11a
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• pp.163-167
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• 2003

In this paper, an air-suspension type RF MEMS inductor is fabricated, and an appropriate de-embedding scheme for 3-dimenstional MEMS structure is applied and verified with inductance calculation algorithm. With the presented de-embedding method, parasitics from contanct pads and feeding lines are effectively and accurately de-embedded using open and short calibration procedure, and only spiral and posts can be characterized as a high-Q inductor structure. The validity of the de-embedding method is verified by the comparison of the measured and calculated inductances of two 1.5 and 2.5 turn square spiral inductors. The open-short de-embedded inductance error is below 5% each case in comparison with the calculated value based on H.M. Greenhouse's algorithm.

• ETRI Journal
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• v.25 no.2
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• pp.65-72
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• 2003

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6" Si wafer with a 25${\mu}m$ thick $SiO_2$ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 ${\Omega}$ coplanar transmission line (W=50${\mu}m$, G=20${\mu}m$). Using benzo cyclo butene (BCB) interlayers and a 10 ${\mu}m$ Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30-120, depending on geometrical parameters and inductance values of 0.35-35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high-speed wireless LAN applications. The chip sizes of the wafer-level-packaged RF IPDs and wire-bondable RF IPDs were 1.0-1.5$mm^2$ and 0.8-1.0$mm^2$, respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand-held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.

• Journal of the Korean Magnetics Society
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• v.11 no.5
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• pp.222-225
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• 2001

The planar type inductors have a good potential for the application of miniaturized low power DC-DC converters. For those high quality application, the reduction of coil loss and also magnetic films which have good high frequency properties are required. Fabricated inductor was consisted of FeTaN/Ti magnetic film and electroplated Cu coil thickness of 100$\mu\textrm{m}$ and $SiO_2$ as a insulating layer. The inductor was designed double rectangular spiral shape for magnetic field highly confining within the device. The measured value of inductance and resistance were 980 nH and 1.7 $\Omega$ at 1 MHz as operating frequency of device. The Q factor is 3.55 at 1 MHz.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.2
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• pp.104-115
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• 2002

Core is the main component of inductor. This core should be classified into around 10 classes according to the value of inductance and Q. The coil should be winded with the outer-boundary of this core by different number of turns. Theses kind of precise inductors would be required in the future environment which PCs and communication devices demand more high speed and lower voltage level. It would be quite unefficient that only one core is classified once a time. There, it will be developed so that 10 cores are classified simultaneously. For the operation of classifying 10 cores once in a time, suppose 10 test instruments could be used. In this case, it would take much cost since a test instrument Is expensive. So, by using only one test instrument, it is really more desirable that this system is developed. Each core classified by 10 different classes is to be stored into the corresponding box through the corresponding rubber hose. 10 cores are passed on a serial line and are placed on each testing slot. Here, each core located at each slot is tested, and then the bowl located on the top of a step motor is moved into the corresponding spot by rotating step motor with some angles. Each bowl connected with the corresponding box through rubber hose. Actually 100 hoses are connected, 10 step motors are rotated at 10 different angles, so the size is really so big, the shape of connecting 100 hoses is so complicated. Therefore it is anticipated that the system would be going to be easily out of ordered. In this paper the main purpose is to make several suggestions to be able to work well in these kinds of being affected by the abnormal operation of motors and the flow of cores.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.10
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• pp.1169-1176
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• 2010

The RF front-end for L1/L2 dual-band Global Positioning System(GPS) receiver is presented in this paper. The RF front-end(down-converter) using low IF architecture consists of a wideband low noise amplifier(LNA), a current mode logic(CML) frequency divider and a I/Q down-conversion mixer with a poly-phase filter for image rejection. The current bleeding technique is used in the LNA and mixer to obtain the high gain and solve the head-room problem. The common drain feedback is adopted for low noise amplifier to achieve the wideband input matching without inductors. The fabricated RF front-end using $0.18{\mu}m$ CMOS process shows a gain of 38 dB for L1 and 41 dB for L2 band. The measured IIP3 is -29 dBm in L1 band and -33 dBm in L2 band, The input return loss is less than -10 dB from 50 MHz to 3 GHz. The measured noise figure(NF) is 3.81 dB for L1 band and 3.71 dB for L2 band. The image rejection ratio is 36.5 dB. The chip size of RF front end is $1.2{\times}1.35mm^2$.