• Journal of electromagnetic engineering and science
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• v.11 no.4
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• pp.257-261
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• 2011

A highly efficient 2.4 GHz rectenna is designed using a harmonic rejection bandpass filter. The rectenna is printed on Rogers Duroid 5880 substrate with ${\varepsilon}_r$=2.2 and a thickness of 1.6 mm. The rectenna consists of a microstrip antenna and high order harmonic rejection bandpass filter, microstrip lowpass filter, and Schottky barrier diode (HSMS2820). The use of a $2^{nd}$ and $3^{rd}$ harmonic rejection microstrip bandpass filter in the rectenna results in high conversion efficiency. The proposed rectenna achieves a RF to DC conversion efficiency of 72.17 % when the received RF power is 63.09 mW.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.7
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• pp.710-716
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• 2007

In this paper, I study on the realization of 900 MHz 1 W power amplifier using a harmonic rejection circuit. The proposed harmonic rejection circuit has improved the harmonic rejection characteristic and overcoming the problems related with frequency reproducibility on the microstrip line. The proposed power amplifier, fabricated by the type of hybrid with the epoxy PCB, was composed of driver stage and power amplifier stage with harmonic rejection circuit. The fabricated power amplifier shows -24 dBc and -30 dBc of harmonic rejection characteristic at 2nd and 3rd harmonic compared with that is not used, respectively and it could be replace the filter located between an output stage and an antenna.

• ETRI Journal
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• v.30 no.2
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• pp.344-346
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• 2008

In this paper, we present a novel oscillator (OSC) design. Bandpass filters, which can suppress harmonics, are incorporated into a co-design with an OSC to improve the OSC phase noise and harmonic rejection. The proposed OSC/bandpass filter co-design achieves a phase noise of -130.1 dBc/Hz/600 kHz and harmonic rejection of 37.94 dB and 40.85 dB for the second and third harmonics, respectively, as compared to results achieved by the OSC before co-design of -101.6 dBc/Hz/600 kHz and 21.28 dB and 19.68 dB. Good agreement between the measured and simulated results is achieved.

• Journal of electromagnetic engineering and science
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• v.14 no.2
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• pp.47-53
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• 2014

This paper presents a high gain and high harmonic rejection low-noise amplifier (LNA) for software-defined radio receiver. This LNA exploits the high quality factor (Q) series resonance technique. High Q series resonance can amplify the in-band signal voltage and attenuate the out-band signals. This is achieved by a source impedance transformation. This technique does not consume power and can easily support multiband operation. The chip is fabricated in a $0.13-{\mu}m$ CMOS. It supports four bands (640, 710, 830, and 1,070MHz). The measured forward gain ($S_{21}$) is between 12.1 and 17.4 dB and the noise figure is between 2.7 and 3.3 dB. The IIP3 measures between -5.7 and -10.8 dBm, and the third harmonic rejection ratios are more than 30 dB. The LNA consumes 9.6 mW from a 1.2-V supply.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.81-89
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• 1996

In this paper, a very efficient CAD algorithm is proposedd where rhodes formulae combined with distributed lowpass prototype filter in order to design the corrugated waveguide harmonic rejection filters accurately. The proposed algorithm resolves effectively the problem of proximity effect without any optimiation or iterative design process by using the internally convexed corrugated structure. A 13-section tapered corrugated lowpass filter has been designed by the proposed algorithm and fabricated. The experimental results are in good agreement with the calculated results.

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.217-221
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• 2016

In this work, open and short stubs that were fabricated on the silicon substrate and for which the periodically arrayed grounded-strip structure (PAGS) was employed were studied along with their basic RF characteristics for an applicability regarding the RF-matching components. The PAGS-employing open and short stubs showed losses that are much lower than that of the conventional stub on the silicon substrate. Concretely, the Q values of the open and short stubs are 9 and 10.2, respectively, while the Q value of the conventional open stub is 2.5. With the use of the PAGS-employing open and short stubs, a highly miniaturized harmonic-rejection filter was also fabricated on the silicon substrate. The filter exhibited a comparatively sound harmonic-suppression characteristic at n × 13 GHz, and its size is 0.1 mm², which is only 7% of the size of the conventional filter on the silicon substrate.

• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.6
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• pp.272-275
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• 2004

A balanced single side-band (SSB) mixer employing a sub-harmonic configuration is designed for up and down conversions in K-band. The designed mixer uses anti-parallel diode (APD) pairs to effectively eliminate even harmonics of the local oscillator (LO) spurious signal. To reduce the odd harmonics of LO at the RF port, we employ a balanced configuration for LO. The fabricated chip shows 12$\pm$2dB of conversion loss and image-rejection ratio of about 20dB for down conversion at RF frequencies of 24-27.5GHz. As an up-conversion mode, the designed chip shows 12dB of conversion loss and image-rejection ratio of 20 ～ 25 dB at RF frequencies of 25 to 27GHz. The odd harmonics of the LO are measured below -37dBc.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.134-137
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• 2008

This paper proposes a novel quadrature VCO(QVCO) based on direct back-gate second harmonic coupling. The QVCO directly couples the current sources of the conventional LC VCOs through the back-gate instead of front-gate to generate quadrature signals. By the second harmonic injection locking, the two LC VCOs can generate quadrature signals without using on-chip transformer, or stability problem that is inherent in the direct front-gate second harmonic coupling. The proposed QVCO is implemented in $0.18{\mu}m$ CMOS technology operating at 2 GHz with 5.0 mA core current consumption from 1.8 V power supply. The measured phase noise of the proposed QVCO is - 63 dBc/Hz at 10 kHz offset, -95 dBc/Hz at 100 kHz offset, and -116 dBc/Hz at 1 MHz offset from the 2 GHz output frequency, respectively. The calculated figure of merit(FOM) is about -174 dBc/Hz at 1 MHz offset. The measured image band rejection is 46 dB which corresponds to the phase error of $0.6^{\circ}$.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.1
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• pp.41-48
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• 2003

In this paper, a new equivalent circuit for a defected ground structure(DGS) is proposed and adapted to design of a power amplifier for performance improvement. The DGS equivalent circuit presented in this paper consists of parallel LC resonator and parallel capacitance to describe the fringing fields due to the etched defects on the metallic ground plane, and also is used to optimize the matching circuit of a power amplifier. A previous research has also used a DGS for harmonic rejection and efficiency improvement of a power amplifier(1), however, there was no exact equivalent circuit analysis. In this paper, we suggest a novel design method and show the performance improvement of a class AB power amplifier by using the equivalent circuit of a DGS applied to output matching circuit. The design method presented in this paper can provide very accurate design results to satisfy the optimum load condition and the desirable harmonic rejection, simultaneously. As a design example, we have designed a 20W power amplifier with and without circuit simulation of DGS, and compared the measurement results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3215-3226
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• 1996

In this paper a K-band harmonic oscillator competitive to ordinary Push-Push type oscillators is introduced. This oscillator is composed of two-X-band dielectric resonance circuits. To favor its harmonic generation, the load effect and the bias effect are studied to allow the maximum harmonic distortion. As results, the dielectric resonated load and the class A bias are used for the 2nd harmonic generation. analytical study for modelling of voltage controlled dielectric resonator is carried out with theoretical background. The performance of the circuit is evaluated by simulation using harmonic balanced method. The novel structure has ont only a voltage tuning circuit but also an output port at fundamental frequency as the function of prescaler for phase lockede loop application on the just single oscillation structure. In experimentation, the output freqneyc of the 2nd harmonic signal is 20.5GHz and the maximum power level of output is +5.5dBm without additional post amplifiers. the harmonic oscillator exhibits -30dBc of high fundamental frequency rejection without added extra filters. The phase noise of -90dBc/Hz at 100kHz off-carrier has been achieved under free running condition, that satisfies phase noise requirement of IESS 308. The proposed oscillator may be utilized as the clean and stable fixed local oscillator in Transmit Block Upconvertor(TBU) or Low oise Block downconvertor(LNB) for K/Ka-band digital communications and satellite broadcastings.