• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.281-284
• /
• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.2
• /
• pp.73-79
• /
• 2011

This paper describes a reset-free delay-locked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop's lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-${\mu}m$ CMOS process, post-layout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 MHz. It occupies 0.04 $mm^2$ and dissipates 16.6 mW at 1.2 GHz.

• Journal of IKEEE
• /
• v.22 no.4
• /
• pp.1158-1162
• /
• 2018

A fast-lock multiplying delay-locked loop (MDLL)-based digital clock frequency multiplier with an anti-harmonic lock capability is presented. The proposed digital frequency multiplier utilizes a new most-significant bit (MSB)-interval search algorithm to achieve fast-locking time without harmonic lock problems. The proposed digital MDLL frequency multiplier is designed in a 65nm CMOS process, and the operating output frequency range is from 1 GHz to 3 GHz. The digital MDLL provides a programmable fractional-ratio frequency multiplication ratios of N/M, where N = 1, 4, 5, 8, 10 and M = 1, 2, 3, respectively. The proposed MDLL consumes 3.52 mW at 1GHz and achieves a peak-to-peak (p-p) output clock jitter of 14.07 ps.

• Proceedings of the KIPE Conference
• /
• 2018.11a
• /
• pp.95-97
• /
• 2018

The power quality of Single Phase Grid-Connected Inverters (GCIs) has received much attention with the increasing number of Distributed Generation (DG) systems. However, the performance of single phase GCIs get degraded due to several factors such as the grid voltage harmonics, the dead time effect, and the turn ON/OFF of the switches, which causes the harmonics at the output of GCIs. Therefore, it is not easy to satisfy the harmonic standards such as IEEE 519 and P1547 without the help of harmonic compensator. To meet the harmonic standards a certain kind of harmonic controller needs to be added to the current control loop to effectively mitigate the low order harmonics. In this paper, the harmonic compensation is performed using a novel robust harmonic compensation method based on Digital Lock-in Amplifier (DLA). In the proposed technique, DLAs are used to extract the amplitude and phase information of the harmonics from the output current and compensate it by using a simple PI controller in the feedforward manner. In order to show the superior performance of the proposed harmonic compensation technique, it is compared with those of conventional harmonic compensation methods in terms of the effectiveness of harmonic elimination, complexity, and implementation. The validity of the proposed harmonic compensation techniques for the single phase GCIs is verified through the experimental results with a 5kW single phase GCI. Index Terms -Single Phase Grid Connected Inverter (SPGCI), Harmonic Compensation Method, Total Harmonic Distortion (THD) and Harmonic Standard.

• Journal of IKEEE
• /
• v.21 no.4
• /
• pp.416-419
• /
• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2012.10a
• /
• pp.259-262
• /
• 2012

This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.25 no.5
• /
• pp.358-368
• /
• 2020

Grid-connected inverters (GCIs) based on renewable energy sources play an important role in enhancing the sustainability of a society. Harmonic standards, such as IEEE 519 and P1547, which require the total harmonic distortion (THD) of the output current to be less than 5%, should be satisfied when GCIs are connected to a grid. However, achieving a current THD of less than 5% is difficult for GCIs with an output filter under a distorted grid condition. In this study, a novel harmonic compensation method that uses a digital lock-in amplifier (DLA) is proposed to eliminate harmonics effectively at the output of GCIs. Accurate information regarding harmonics can be obtained due to the outstanding performance of DLA, and such information is used to eliminate harmonics with a simple proportional-integral controller in a feedforward manner. The validity of the proposed method is verified through experiments with a 5 kW single-phase GCI connected to a real grid.

• Proceedings of the KIPE Conference
• /
• 2019.07a
• /
• pp.77-79
• /
• 2019

Islanding detection is one of the most important issues for the distributed generation (DG) systems connected to the power grid. The conventional passive islanding detection methods inherently have a non-detection zone (NDZ), and active islanding detection methods may deteriorate the power quality of a power system. This paper proposes a novel hybrid islanding detection method based on Digital Lock-In Amplifier with no NDZ by monitoring the harmonics present in the grid. Proposed method detects islanding by passively monitoring the grid voltage harmonics and verify it by injecting small perturbation for only three-line cycles. Unlike FFT for the harmonic extraction, DLA HC have lower computational burden, moreover, DLA can monitor harmonic in real time, whereas, FFT has certain propagation delay. The simulation results are presented to highlight the effectiveness of the proposed technique. In order to prove the performance of the proposed method it is compared with several passive islanding detection methods. The experimental results confirm that the proposed method exhibits outstanding performance as compared to the conventional methods.

• Ocean and Polar Research
• /
• v.33 no.3
• /
• pp.309-319
• /
• 2011

This is a preliminary study of the feasibility of obtaining reliable tidal current harmonic constants, using one month of current observations, to verify the accuracy of a tidal model. An inference method is commonly used to separate out the tidal harmonic constituents when the available data spans less than a synodic period. In contrast to tidal constituents, studies of the separation of tidal-current harmonics are rare, basically due to a dearth of the long-term observation data needed for such experiments. We conducted concurrent and monthly harmonic analyses for tidal current velocities and heights, using 2 years (2006 and 2007) of current and sea-level records obtained from the Tidal Current Signal Station located in the narrow waterway in front of Incheon Lock, Korea. Firstly, the l-year harmonic analyses showed that, with the exception of $M_2$ and $S_2$ semidiurnal constituents, the major constituents were different for the tidal currents and heights. $K_1$, for instance, was found to be the 4th major tidal constituent but not an important tidal current constituent. Secondly, we examined monthly variation in the amplitudes and phase-lags of the $S_2$ and $K_1$ current-velocity and tide constituents over a 23-month period. The resultant patterns of variation in the amplitudes and phase-lags of the $S_2$ tidal currents and tides were similar, exhibiting a sine curve form with a 6-month period. Similarly, variation in the $K_1$ tidal constant and tidal current-velocity phase lags showed a sine curve pattern with a 6-month period. However, that of the $K_1$ tidal current-velocity amplitude showed a somewhat irregular sine curve pattern. Lastly, we investigated and tested the inference methods available for separating the $K_2$ and $S_2$ current-velocity constituents via monthly harmonic analysis. We compared the effects of reduction in monthly variability in tidal harmonic constants of the $S_2$ current-velocity constituent using three different inference methods and that of Schureman (1976). Specifically, to separate out the two constituents ($S_2$ and $K_2$), we used three different inference parameter (i.e. amplitude ratio and phase-lag diggerence) values derived from the 1-year harmonic analyses of current-velocities and tidal heights at (near) the short-term observation station and from tidal potential (TP), together with Schureman's (1976) inference (SI). Results from these four different methods reveal that TP and SI are satisfactorily applicable where results of long-term harmonic analysis are not available. We also discussed how to further reduce the monthly variability in $S_2$ tidal current-velocity constants.

• The Transactions of the Korean Institute of Electrical Engineers B
• /
• v.51 no.1
• /
• pp.23-33
• /
• 2002

A hysteresis control is widely used to control output current of inverter. A hysteresis bandwidth is affected by system parameters such as source voltage, device on/off time, load inductance and resistance. The frequency limiter is used to protect switching devices overload. In the conventional hysteresis controller, a lock-out circuit with D-latch and timer is used to device protection circuit. But switching delay time and harmonic components are appeared in output current. In this paper the performance of lock-out circuit is tested, and new circuit for switching device fault protection is proposed ad it's performance is simulated.