• Smart Structures and Systems
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• v.5 no.4
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• pp.469-482
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• 2009

The emerging sensor-based structural health monitoring (SHM) technology has a potential for cost-effective maintenance of aging civil infrastructure systems. The author proposes to integrate continuous and global monitoring using on-structure sensors with targeted local non-destructive evaluation (NDE). Significant technical challenges arise, however, from the lack of cost-effective sensors for monitoring spatially large structures, as well as reliable methods for interpreting sensor data into structural health conditions. This paper reviews recent efforts and advances made in addressing these challenges, with example sensor hardware and health monitoring software developed in the author's research center. The hardware includes a novel fiber optic accelerometer, a vision-based displacement sensor, a distributed strain sensor, and a microwave imaging NDE device. The health monitoring software includes a number of system identification methods such as the neural networks, extended Kalman filter, and nonlinear damping identificaiton based on structural dynamic response measurement. These methods have been experimentally validated through seismic shaking table tests of a realistic bridge model and tested in a number of instrumented bridges and buildings.

• ETRI Journal
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• v.32 no.3
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• pp.370-379
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• 2010

In this paper, we propose efficient masking methods for ARIA and AES. In general, a masked S-box (MS) block can be constructed in different ways depending on the implementation platform, such as hardware and software. However, the other components of ARIA and AES have less impact on the implementation cost. We first propose an efficient masking structure by minimizing the number of mask corrections under the assumption that we have an MS block. Second, to make a secure and efficient MS block for ARIA and AES, we propose novel methods to solve the table size problem for the MS block in a software implementation and to reduce the cost of a masked inversion which is the main part of the MS block in the hardware implementation.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.527-528
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• 2006

In this paper, we propose an IP design and implementation of System on a chip(SoC) for Discrete Cosine Transform (DCT) and Discrete Wavelet Transform (DWT) processor using adder-based DA(Adder-based Distributed Arithmetic). To reduced hardware cost and to improve operating speed, the combined DCT/ DWT processor used the bit-serial method and DA module. The transform of coefficient equation result in reduction in hardware cost and has a regularity in implementation. We use Verilog-HDL and Xilinx ISE for simulation and implement FPGA on SoCMaster-3.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.1
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• pp.62-68
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• 2007

H.264 video compression in digital multimedia broadcasting (DMB) shows significantly high compression ratio over conventional algorithms, while its required hardware cost and power consumption are also $3{\sim}5$ times larger. Consequently, low-hardware-cost and low-power H.264 decoder SoC is essential for commercial digital multimedia broadcasting terminals. This paper describes low-power design and implementation of core blocks in H.264 decoder SoC.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.485-499
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• 2021

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.

• Current Optics and Photonics
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• v.7 no.6
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• pp.683-691
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• 2023

A typical terahertz time-domain spectroscopy system requires large, expensive, and heavy hardware such as a lock-in amplifier and a function generator. In this study, we replaced the lock-in amplifier and the function generator with a single sound card built into a typical desktop computer to significantly reduce the system size, weight, and cost. The sound card serves two purposes: 1 kHz chopping signal generation and raw data acquisition. A unique software lock-in (Python coding program to eliminate noise from raw data) method was developed and successfully extracted THz time-domain signals with a signal-to-noise ratio of ~40,000 (the intensity ratio between the peak and average noise levels). The built-in sound card with the software lock-in method exhibited sufficiently good performance compared with the hardware-based method.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.6
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• pp.176-185
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• 1996

In this paper, we present the modified CMA (constant modulus algorithm) and LMS (least mean square) algorithms for digiCipher system with reduced hardware cost, in which the pipelined architecture is employed. They yield the performance comparable to that using floating-point operations. We show the effecstiveness of the proposed architecture through the implementation results using VHDL.

• Proceedings of the KIEE Conference
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• 1997.07c
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• pp.930-932
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• 1997

Logic Based Expert System (LBES) has the advantage of real-time inference. This paper shows a LBES for fault diagnosis of power system and proposes the hardware implementation of LBES. Besides, having a power system topology in memory chip, proposed system is apt to be applicable to other system with low changing cost.

• Korean Journal of Remote Sensing
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• v.8 no.1
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• pp.59-69
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• 1992

The IMAPRO sotfware package was mainly focused to provide an algorithm which is capable of displaying various color composite images on IBM PC, VGA(Video Graphic Array) card with no special hardware. It displays the false color images using a low-cost eight-bit place refresh buffer. This produces similar quality to the one obtained from image board with three eight-bit plane. Also, it provides user friendly menu driven method for the user who are not familier with technical knowladge of image processing. It may prove useful for universities, institute and private company where expensive hardware is not available.

• The Transactions of the Korea Information Processing Society
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• v.7 no.6
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• pp.1810-1817
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• 2000

The purpose of this research is to develop an estimation model for information systems operating costs. Current cost estimation practices and types of sytem management projects have been reviewed an analyses. Typical operating project types of information systems are determined. They are application system operation, help disk operation, network management and operation, and hardware management. For each type of projects, cost factors ar identified and a structure of cost estimation model is defined. Cost estimation models have been constructed and tested by 24 real operation projects data. Statistical analysis shows derived models are statistically significant. User groups' opinion on these draft cost estimation model has been surveyed and summarized. The results of this research can be used as a cornerstone for future research on operating cost estimation, and for cost estimation guideline of information systems operation projects.