• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.212-212
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• 2013

We fabricate and characterize top gate Graphene transistor using aluminum oxide as a gate insulator by atomic layer deposition (ALD). It is found that due to absence of functional group and dangling bonds, ALD of metal oxide is difficult on Graphene. Here we used 4-mercaptopheneol as a functionalization layer on Graphene to facilitate uniform oxide coverage. Contact angle measurement and Atomic force microscopy were used to confirm uniform oxide coverage on Graphene. Raman spectroscopy revealed that functionalization with 4-mercaptopheneol does not induce any defect peak on Graphene. Our device shows mobility values of 4,000 $cm^2/Vs$ at room temperature which also suggest top gate stack does not significantly increase scattering. The noncovalent functionalization method is non-destructive and can be used to grow ultra-thin dielectric for future Graphene applications.

• Journal of Environmental Impact Assessment
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• v.19 no.3
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• pp.231-245
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• 2010

The the purpose of this study was to analyze of the vegetation structure and phytosociological changes in the area adjacent to GeumJeong Mountain Fortress for fifteen years. The result of this study was as follows; Of the 8 quadrates, site of the North Gate 2 was having a highest in the number of extinct trees, 15 kinds. This is probably due to trampling effect caused by climbers' steps. Site of the West Gate 1 and South gate 1 each had 8 kinds of extinct trees, respectively. The number of newly appeared trees was highest at site of the North Gate 1, (8 kinds) followed by the sites of South gate 1 and South gate 2, respectively (5 kinds). The highest decrease in number of tree species was observed in North Gate 1, therefore, there is a strong relationship between vegetation diversity and the number of users of the available spaces. In order to revitalize the unstable vegetation structure of the Area Adjacent to GeumJeong Mountain Fortress, Robinia pseudo-acacia has to be well maintained in the shrub tree layer, and vines, such as Smilax china, Humulus japonicus, and Pueraria thungergiana, should be removed. To recover natural vegetation, dead leaf layer should be protected, and more shrub trees need to be planted. In the understory and shrub tree layer, multi layer tree planting is highly recommended to recover natural vegetation and increase tree diversity. In order to improve bad soil condition caused by trampling effect of recreational users, special treatments to the soil structure are required, such as mulching and raking soil. Also, depending on its soil damage from users trampling, the areas in the park should be divided into usable areas and user limited areas by the sabbatical year system. To improve the soil acidity due to acidic rain, soil buffering ability should be improved by activating microorganisms in the soil by using lime and organic material.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.271-276
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• 2017

The triple-gate tunnel FETs encapsulated with an epitaxial layer (EL TFETs) is proposed to lower the subthreshold swing of the TFETs. Furthermore, the band-to-band tunneling based on the maximum electric-field can occur thanks to the epitaxial layer wrapping the Si fin. The performance and mechanism of the EL TFETs are compared with the previously proposed TFET based on simulation.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.366-366
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• 2013

건식 박막증착 공정인 플라즈마 중합법을 이용하여 유기 재료인 Styrene을 절연 박막으로 제작하였다. 플라즈마 중합된 Styrene (ppS) 절연 박막의 정밀한 공정 제어를 위해 bubbler와 circulator를 이용하여 습식 공정과 비교하여도 절연 특성이 뛰어난 pps 절연 박막을 증착하고, 이를 활용하여 gate 전극으로 ITO, insulator layer로 pps, floating gate로 Au, tunneling layer로 ppMMA와 pps, semiconductor로 Pentacene, source/drain 전극으로 Au를 사용한 비휘발성 메모리 소자를 제작하였다. ppMMA와 pps의 서로 다른 tunneling layer의 두께 변화에 따른 비휘발성 메모리 특성 변화를 연구하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1103-1106
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• 2006

We have presented a comprehensive study on threshold voltage $(V_{th})$ control of organic thin-film transistors (OTFTs) with dual-gate structure. The fabrication of dual-gate pentacene OTFTs using plasma-enhanced atomic layer deposited (PEALD) 150 nm thick $Al_2O_3$ as a bottom gate dielectric and 300 nm thick parylene or PEALD 200 nm thick $Al_2O_3$ as both a top gate dielectric and a passivation layer is reported. The $V_{th}$ of OTFT with 300 nm thick parylene as a top gate dielectric is changed from 4.7 V to 1.3 V and that with PEALD 200 nm thick $Al_2O_3$ as a top gate dielectric is changed from 1.95 V to -9.8 V when the voltage bias of top gate electrode is changed from -10 V to 10 V. The change of $V_{th}$ of OTFT with dual-gate structure has been successfully understood by an analysis of electrostatic potential.

• Journal of IKEEE
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• v.24 no.4
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• pp.1167-1171
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• 2020

In this work, we proposed a graded gate-doping structure to alleviate an electric field in p-GaN gate layer in order to improve the reliability of normally-off GaN power devices. In a TCAD simulation by Silvaco Atlas, a distribution of the graded p-type doping concentration was optimized to have a threshold voltage and an output current characteristics as same as the reference device with a uniform p-type gate doping. The reduction of an maximum electric field in p-GaN gate layer was observed and it suggests that the gate reliability of p-GaN gate HFETs can be improved.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.351.1-351.1
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• 2014

In this study, we prepared the solution-based In-Ga-Zn oxide thin film transistors (IGZO TFTs) of multistacked active layer and characterized the gate bias instability by measuring the change in threshold voltage caused by stacking. The solutions for IGZO active layer were prepared by In:Zn=1:1 mole ratio and the ratio of Ga was changed from 20% to 30%. The TFTs with multistacked active layer was fabricated by stacking single, double and triple layers from the prepared solutions. As the number of active layer increases, the saturation mobility shows the value of 1.2, 0.8 and 0.6 (). The electrical properties have the tendency such as decreasing. However when gate bias VG=10 V is forced to gate electrode for 3000 s, the threshold voltage shift was decreased from 4.74 V to 1.27 V. Because the interface is formed between the each layers and this affected the current path to reduce the electrical performances. But the uniformity of active layer was improved by stacking active layer with filling the hole formed during pre-baking so the stability of device was improved. These results suggest that the deposition of multistacked active layer improve the stability of the device.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.341-341
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• 2012

Recently, oxide semi-conductor materials have been investigated as promising candidates replacing a-Si:H and poly-Si semiconductor because they have some advantages of a room-temperature process, low-cost, high performance and various applications in flexible and transparent electronics. Particularly, amorphous indium-gallium-zinc-oxide (a-IGZO) is an interesting semiconductor material for use in flexible thin film transistor (TFT) fabrication due to the high carrier mobility and low deposition temperatures. In this work, we demonstrated improvement of flexibility in IGZO TFTs, which were fabricated on polyimide (PI) substrate. At first, a thin poly-4vinyl phenol (PVP) layer was spin coated on PI substrate for making a smooth surface up to 0.3 nm, which was required to form high quality active layer. Then, Ni gate electrode of 100 nm was deposited on the bare PVP layer by e-beam evaporator using a shadow mask. The PVP and $Al_2O_3$ layers with different thicknesses were used for organic/inorganic multi gate dielectric, which were formed by spin coater and atomic layer deposition (ALD), respectively, at $200^{\circ}C$. 70 nm IGZO semiconductor layer and 70 nm Al source/drain electrodes were respectively deposited by RF magnetron sputter and thermal evaporator using shadow masks. Then, IGZO layer was annealed on a hotplate at $200^{\circ}C$ for 1 hour. Standard electrical characteristics of transistors were measured by a semiconductor parameter analyzer at room temperature in the dark and performance of devices then was also evaluated under static and dynamic mechanical deformation. The IGZO TFTs incorporating hybrid gate dielectrics showed a high flexibility compared to the device with single structural gate dielectrics. The effects of mechanical deformation on the TFT characteristics will be discussed in detail.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.118-118
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• 2011

The Nano-Floating Gate Memory(NFGM) devices with ZnO:Cu thin film embedded in Al2O3 and AlOx-SAOL were fabricated and the electrical characteristics were evaluated. To further improve the scaling and to increase the program/erase speed, the high-k dielectric with a large barrier height such as Al2O3 can also act alternatively as a blocking layer for high-speed flash memory device application. The Al2O3 layer and AlOx-SAOL were deposited by MLD system and ZnO:Cu films were deposited by ALD system. The tunneling layer which is consisted of AlOx-SAOL were sequentially deposited at $100^{\circ}C$. The floating gate is consisted of ZnO films, which are doped with copper. The floating gate of ZnO:Cu films was used for charge trap. The same as tunneling layer, floating gate were sequentially deposited at $100^{\circ}C$. By using ALD process, we could control the proportion of Cu doping in charge trap layer and observe the memory characteristic of Cu doping ratio. Also, we could control and observe the memory property which is followed by tunneling layer thickness. The thickness of ZnO:Cu films was measured by Transmission Electron Microscopy. XPS analysis was performed to determine the composition of the ZnO:Cu film deposited by ALD process. A significant threshold voltage shift of fabricated floating gate memory devices was obtained due to the charging effects of ZnO:Cu films and the memory windows was about 13V. The feasibility of ZnO:Cu films deposited between Al2O3 and AlOx-SAOL for NFGM device application was also showed. We applied our ZnO:Cu memory to thin film transistor and evaluate the electrical property. The structure of our memory thin film transistor is consisted of all organic-inorganic hybrid structure. Then, we expect that our film could be applied to high-performance flexible device.----못찾겠음......

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.6
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• pp.1123-1127
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• 2009

This paper expands the scope of application of the thin film transistor (TFT) in which it is used as the switching element by making the amorphous silicon TFT with the non-volatile memory device,. It is the thing about the amorphous silicon non-volatile memory device which is suitable to an enlargement and in which this uses the additionally cheap substrate according to the amorphous silicon use. As to, the amorphous silicon TFT non-volatile memory device is comprised of the glass substrates and the gate, which evaporates on the glass substrates and in which it patterns the first insulation layer, in which it charges the gate the floating gate which evaporates on the first insulation layer and in which it patterns and the second insulation layer in which it charges the floating gate, and the active layer, in which it evaporates the amorphous silicon on the second insulation layer the source / drain layer which evaporates the n+ amorphous silicon on the active layer and in which it patterns and the source / drain layer electrode in which it evaporates on the source / drain layer.