• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.12
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• pp.1-9
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• 2001

In the APON(ATM Passive Optical Network), the transmission of the upstream traffic is based on a TDMA(Time Division Multiple Access) method that an OLT(Optical Line Termination) permits ONUs(Optical Network Units) sending cells by allocating time slots. Because the upstream is not a streaming mode, the cell synchronizer has to be operated in the burst mode. Also, the cell phase monitor is required to prevent collisions between cells which are transmitted by multiple ONUs through a single optical fiber. In this paper, a TDMA burst cell synchroniser is implemented with the FPGA(Field Programmable Gate Array) being used in the APON based on G.983.1 for transmitting upstream cells. It has two main functions which are the upstream data recovery and the phase monitoring. The former is to recover the upstream data and clock in the OLT by seeking the preamble which is the overhead of the upstream time slot and by aligning the phase of the bit and cell with the system clock. The latter is to provide the information to the ONU to compensate for the equalization delay by monitoring continuously the phase difference between adjacent cells to avoid the cell collision on the upstream.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.131-131
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• 2009

Silicon Carbide (SiC) is a material with a wide bandgap (3.26eV), a high critical electric field (~2.3MV/cm), a and a high bulk electron mobility ($\sim900cm^2/Vs$). These electronic properties allow high breakdown voltage, high-speed switching capability, and high temperature operation compared to Si devices. Although various SiC DMOSFET structures have been reported so far for optimizing performances, the effect of channel dimension on the switching performance of SiC DMOSFETs has not been extensively examined. This paper studies different channel dimensons ($L_{CH}$ : $0.5{\mu}m$, $1\;{\mu}m$, $1.5\;{\mu}m$) and their effect on the the device transient characteristics. The key design parameters for SiC DMOSFETs have been optimized and a physics-based two-dimensional (2-D) mixed device and circuit simulator by Silvaco Inc. has been used to understand the relationship. with the switching characteristics. To investigate transient characteristic of the device, mixed-mode simulation has been performed, where the solution of the basic transport equations for the 2-D device structures is directly embedded into the solution procedure for the circuit equations. We observe an increase in the turn-on and turn-off time with increasing the channel length. The switching time in 4H-SiC DMOSFETs have been found to be seriously affected by the various intrinsic parasitic components, such as gate-source capacitance and channel resistance. The intrinsic parasitic components relate to the delay time required for the carrier transit from source to drain. Therefore, improvement of switching speed in 4H-SiC DMOSFETs is essential to reduce the gate-source capacitance and channel resistance.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.60-60
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• 2003

디자인 룰에 의해 Gate Length 가 100nm 이하로 줄어듦에 따라 Gate delay 감소와 Switch speed 향상을 위해 보다 더 큰 drive current 를 요구하게 되었다. 본 연구는 dirve current 를 증가시키기 위해 고안된 Strained Si substrate 를 만들기 위한 SiGe layer 성장에 관한 연구이다. SiGe layer를 성장시킬 때 SiH$_4$ gas와 GeH$_4$ gas를 furnace에 flow시켜 Chemical 반응에 의해 Si Substrate를 성장시키는 LPCVD(low pressure chemical vapor depositio)법을 사용하였고 SIMS와 nanospec을 이용하여 박막 두께 및 Ge concentration을 측정하였고, AFM으로 surface의 roughness를 측정하였다. 본 연구에서 우리는 10,20,30,40%의 Ge concentration을 갖는 10nm 이하의 SiGe layer를 얻기 위하여 l0nm 이하의 fixed 된 두께로 SiGe layer를 성장시킬 때 temperature, GeH$_4$ gas pre-flow, SiH$_4$ 와 GeH$_4$의 gas ratio를 변화시켜 성장시킨 후 Ge 의 concentration과 실제 형성된 두께를 측정하였고, SiGe의 mole fraction의 변화에 따른 surface의 roughness 를 측정하였다. 그 결과 10 nm의 두께에서 temperature, GeH$_4$ gas pre-flow, SiH$_4$ 와 GeH$_4$ 의 gas ratio의 변화와 Ge concentration 과의 의존성을 확인 할 수 있었고, SiGe 의 mole traction이 증가하였을 때 surfcace의 roughness 가 증가함을 알 수 있었다. 이 연구 결과는 strained Si 가 가지고 있는 strained Si 내에서 n-FET 와 P-FET사이의 불균형에 대한 해결과 좀 더 발전된 형태인 fully Depleted Strained Si 제작에 기여할 것으로 보인다.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.35-43
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• 2006

In the paper, we propose a new method for power optimization that uses path balancing based on stochastic estimation of glitch in Statistical Static Timing Analysis (SSTA). The proposed method estimates the probability of glitch occurrence using tightness probability of each node in timing graph. In addition, we propose efficient gate sizing technique for glitch reduction using accurate calculation of sizing effect in delay considering probability of glitch occurrence. The efficiency of proposed method has been verified on ISCAS85 benchmark circuits with $0.16{\mu}m$ model parameters. Experimental results show up to 8.6% of accuracy improvement in glitch estimation and 9.5% of optimization improvement.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.510-520
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• 2011

In this paper, we propose a new multiplication algorithm for primitive polynomial with all 1 of coefficient in case that m is odd and even on finite fields $GF(3^m)$, and compose the multiplier with parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $(m+1)^2$ same basic cells that have a mod(3) addition gate and a mod(3) multiplication gate. Since the basic cells have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $T_A+T_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of the Korea Society of Computer and Information
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• v.18 no.2
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• pp.9-17
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• 2013

In this paper, we propose a new multiplication algorithm for two polynomials using primitive polynomial with all 1 of coefficient on finite fields GF($2^m$), and design the multiplier with high-speed parallel input-output module structure using the presented multiplication algorithm. The proposed multiplier is designed $m^2$ same basic cells that have a 2-input XOR gate and a 2-input AND gate. Since the basic cell have no a latch circuit, the multiplicative circuit is very simple and is short the delay time $D_A+D_X$ per cell unit. The proposed multiplier is easy to extend the circuit with large m having regularity and modularity by cell array, and is suitable to the implementation of VLSI circuit.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.321-327
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• 2006

This paper presents low power and high frequency design of instructions using ad-hoc techniques at transistor level for full custom and semi-custom ASIC(Application Specific Integrated Circuit) designs. The proposed design has been verified at high level using Verilog-HDL and simulated using ModelSim for the logical correctness. It is then observed at the layout level using LASI using $0.25{\mu}m$ technology and analyzed for timing characteristic under Win-spice simulation environment. The result shows the significant reduction up to $35\%$ in the power consumption by any general purpose processor like RISC or CISC. A significant reduction in the propagation delay is also observed. increasing the frequency for the fetch and execute cycle for the CPU, thus increasing the overall frequency of operation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.2
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• pp.430-439
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• 2004

This paper describes a design of 8192/2048-point FFT/IFFT processor (CFFT8k2k), which performs multi-carrier modulation/demodulation in OFDM-based DVB-T receiver. Since a large size FFT requires a large buffer memory, two design techniques are considered to achieve memory-efficient implementation of 8192-point FFT/IFFT. A hybrid structure, which is composed of radix-4 single-path delay feedback (R4SDF) and radix-4 single-path delay commutator (R4SDC), reduces its memory by 20% compared to R4SDC structure. In addition, a memory reduction of about 24% is achieved by a novel two-step convergent block floating-point scaling. As a result, it requires only 57% of memory used in conventional design, reducing chip area and power consumption. The CFFT8k2k core is designed in Verilog-HDL, and has about 102,000 Bates, RAM of 292k bits, and ROM of 39k bits. Using gate-level netlist with SDF which is synthesized using a $0.25-{\um}m$ CMOS library, timing simulation show that it can safely operate with 50-MHz clock at 2.5-V supply, resulting that a 8192-point FFT/IFFT can be computed every 164-${\mu}\textrm{s}$. The functionality of the core is fully verified by FPGA implementation, and the average SQNR of 60-㏈ is achieved.