A Low Power FPGA Architecture using Three-dimensional Structure

3차원 구조를 이용한 저전력 FPGA 구조

  • 김판기 (연세대학교 프로세서연구실) ;
  • 이형표 (연세대학교 프로세서연구실) ;
  • 김현필 (연세대학교 프로세서연구실) ;
  • 전호윤 (연세대학교 프로세서연구실) ;
  • 이용석 (연세대학교 프로세서연구실)
  • Published : 2007.12.15

Abstract

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

Field-Programmable Gate Arrays는 사용자가 프로그램이 가능한 혁신적인 대규모 집적 회로이며 값싸고 빠르게 주문자가 원하는 VLSI 구현할 수 있는 장점을 가지고 있다. 그러나 특정 목적의 프로그램의 속도가 증가했을 때 FPGA가 연산하는 동안의 전력 소모와 연결선의 지연이 FPGA를 프로그램 하는데 중요한 문제점이 된다. 특히 기존 구조에서 사용되는 내부연결선이 전체 FPGA의 전력 중 65%를 소모한다. 이로 인하여 내부연결선이 전력 소모에 큰 영향을 주기 때문에 배선 시 연결선의 길이와 블록 간의 연결선을 줄임으로써 전력 소모를 줄일 수 있다. 배선 시 내부연결선을 줄이기 위한 방안으로 3차원 FPGA가 제안되었다. 하지만 구조의 복잡해짐으로써 오히려 스위치에서 물리적인 연결선들은 더욱 증가하고 스위치의 면적이 증가하는 문제점을 가지게 되었다. 본 논문에서는 복잡성을 낮추어서 물리적인 내부 연결선의 길이를 줄이고, 배선시의 연결선의 길이를 3차원 FPGA만큼 줄일 수 있는 FPGA구조를 제안한다. 그리고 ISE 의 FPGA Editor와 배선 시 길이를 예측하는 프로그램을 사용하여 Xilinx사의 Virtex II FPGA와 3D FPGA의 연결선 구성을 비교한다.

Keywords

References

  1. E. Boemo, G. Gonzzalez de Rivera, S. Lopez-Buedo, and J. M. Meneses. 'Some notes on power management on FPGA-based systems,' Field-Programmable Logic and Applications, pp. 149-157, Aug. 1995
  2. A. Lesea, M. Alexander, 'Powering Xilinx FPGAs,' XILINX.COM
  3. Alexander M.J. , Cohoon J.P., Colflesh J.L. Karro J., Robins G., 'Three-dimensional field-programmable gate arrays,' ASIC Conference and Exhibit, Proceedings of the Eighth Annual IEEE International, Vol., Iss., 18-22, Sep. 1995, pp. 253-256, 1995
  4. Ababei, C., Mogal, H., and Bazargan, K. 'Threedimensional place and route for FPGAs,' In Proceedings of the 2005 Conference on Asia South Pacific Design Automation, Shanghai, China, January 18-21, 2005
  5. http://www.x2e.de/virtex/virtex_x2e.html
  6. www.xilinx.com
  7. http://www.xilinx.com/xapp/xapp151.pdf
  8. S. Bilavarn, G. Gogniat, J. L. Philippe, 'Area Time Power Estimation for FPGA Based Designs at a Behavioral Level,' ICECS, Beyrouth, December 2000
  9. M. Buhler, M. Papesch, K. Kapp, U. G. Baitinger, 'Efficient switching activity simulation under a real delay model using a bitparallel approach,' Proceedings of the conference on Design, automation and test in Europe, Jan. 1999
  10. A. Lesea, M. Alexander, 'Powering Xilinx FPGAs,' http://www.xilinx.com/xapp/xapp158.pdf, XILINX.COM
  11. E. A. Kusse, 'Analysis and circuit design for a low power programmable logic modules,' Master's thesis, Dept. of Electrical Engineering and Computer Science, University of California at Berkeley, 1998
  12. Varghese George, Hui Zhang, and Jan Rabaey, 'The Design of a Low Energy FPGA,' International Symposium on Low power Electronics and Design, 1999
  13. A. Rahman, A. Fan, and R. Reif. 'Comparison of key performance metrics in two- and three-dimensional integrated circuits,' Interconnect Technology Conference, pp. 18-20, Burlingame, CA, USA, 2000
  14. A. Fan and R. Reif. 'Three-dimensional integration with copper wafer bonding,' In Interconnect Technology Conference, pp. 18-20, 2000
  15. Cahill, C. 외 12명, 'Thermal characterization of vertical multichip modules MCM-V,' Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on, Vol.18, No.4, pp. 765-772, Dec 1995 https://doi.org/10.1109/95.477462
  16. M. Leeser, W. M. Meleis, M. M. Vai, S. Chiricescu, W. Xu, and P. M. Zavracky, 'Rothko:3 A three-dimensional FPGA,' IEEE Design and Test of Computers, Vol. 15, pp. 16.23, Jan.-Mar. 1998 https://doi.org/10.1109/54.655178
  17. Lesser, M., Meleis, W.M., Vai, M.M., and Zavracky, P.M. 'Rothko: A Three Dimensional FPGA Architecture, Its Fabrication, and Design Tools,' Field-Programmable Logic and Applications, 1997
  18. Meleis, W., Leeser, M., Zavracky, P., and Vai, M., 'Architectural Design of a Three Dimensional FPGA,' IEEE Seventeenth Conference on Advanced Research in VLSI, pp. 256-268, 1997
  19. John E. Karro, 'Algorithmic and Theoretical Problems Related to the Physical Design of Three Dimensional Field Programmable Gate Arrays,' thesis of Ph.D., Univ. of Vireginia, USA, Aug. 2000
  20. Karro, J., Cohoon, J.P., 'A Spiffy tool for the simultaneous placement and global routing for three-dimensional field-programmable gate arrays,' VLSI, 1999. Proceedings. Ninth Great Lakes Symposium on, pp. 230-231, 4-6 Mar. 1999