• 한국농공학회:학술대회논문집
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• 한국농공학회 2005년도 학술발표논문집
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• pp.306-312
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• 2005

Gates for the purpose of drainage are classified following the types of structure as: Radial Gate, Sluice Gate, Rolling Gate, Drum Gate. In many cases of the reclamation project the sluice type of gates are applied. Different from this general trend, however the radial type of gate was adopted in the Saemangeum project. In this case the discharge coefficients which are used for the sluice type of gate was applied. To estimate the correct amount of discharge which will be evacuated through the gates, therefore the proper discharge coefficients should be estimated before the operation of the gates. The discharge coefficients were estimated through the physical hydraulic modeling, and we got the results as: $0.72{\sim}0.84$ for the submerged condition on the both sides of upstream and downstream, $0.62{\sim}0.83$ for the free surface condition on the downtream side only, and $1.04{\sim}1.12$ for the free surface condition on the both sides of upstream and downstream. The discharge coefficients obtained from the experiments are greater than those of the sluice gates in the design criteria. From the results of the study we may expect that in the Saemangeum project the radial gates could evacuate larger amount of discharge than the originally designed discharge, so that we may sure that the Saemangeum gates have enough capability to control the evacuation of water not only in the usual period but also in the flooding season.

• 한국전기전자재료학회논문지
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• 제24권8호
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• pp.609-615
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• 2011

This paper is studied for the improvement of the characteristics of gate oxide with 3-nm-thick gate oxide by deuterium ion implantation methode. Deuterium ions were implanted to account for the topography of the overlaying layers and placing the D peak at the top of gate oxide. A short anneal at forming gas to nitrogen was performed to remove the damage of D-implantation. We simulated the deuterium ion implantation to find the optimum condition by SRIM (stopping and range of ions in matter) tool. We got the optimum condition by the results of simulation. We compare the electrical characteristics of the optimum condition with others terms. We also analyzed the electrical characteristics to change the annealing conditions after deuterium ion implantation. The results of the analysis, the breakdown time of the gate oxide was prolonged in the optimum condition. And a variety of annealing, we realized the dielectric property that annealing is good at longer time. However, the high temperature is bad because of thermal stress.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2004년도 춘계종합학술대회
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• pp.661-663
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• 2004

본 논문에서는 main gate와 side gate를 갖는 double gate MOSFET의 C-V 특성을 조사하기 위하여 side gate 길이와 side gate 전압을 변화시켜 조사하였다. Main gate 전압은 -5V에서 +5V까지 변화시켰으며, main gate 길이가 50nm, side gate 길이가 70nm, side gate 전압이 3V, drain 전압이 2V일때 우수한 C-V 특성을 얻었다. 이 때 소자의 특성 분석을 위해 ISE-TCAD를 사용하여 시뮬레이션 하였다.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2003년도 춘계학술대회논문집
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• pp.363-370
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• 2003

Shrinkage of injection molded parts is different form operational conditions of injection molding such as injection temperature, injection pressure and mold temperature, and mold design such as gate size. It is also various for different resins which have crystalline structure or not. In this study part shrinkage was investigated for various operational condition and resins; PBT for crystalline polymer, and PC and PMMA for amorphous polymer was used in experiment. Crystalline polymer shows higher part shrinkage by about three times than amorphous polymer. Part shrinkage increased as injection temperature and mold temperature increased and injection pressure decreased. Part shrinkage decreased as gate size increased since the pressure delivery is mush easier for large gate size. Part shrinkage according to the gate location was that the position in the part with close to the gate showed large shrinkage and this phenomenon might be occurred by residual stress.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집 Vol.14 No.1
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STD structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters. we studied the correlation between CMP thickness of STI using high selectivity slurry. DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased. the N-poly foot is deteriorated. and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point,, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by $100\AA$. 3.2 $u\AA$ of IDSN is getting better in base 1 condition. In POE 50% condition. 1.7 $u\AA$ is improved. and 0.7 $u\AA$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 소성∙가공
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• 제15권8호
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• pp.628-632
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• 2006

The gate mark in injection molded part is a kind of surface defects. The formation of gate mark has been investigated in this study. SEM photographs and surface roughness have been examined to study gate mark. The specimens were molded for various injection conditions, such as injection temperature, mold temperature, and injection speed. Gate diameter and mold surface condition were also molding variables. Gate marks were reduced as injection speed and mold temperature increased. Gate diameter and injection temperature did not affect the gate marks. No etching of mold surface showed no gate marks for any molding conditions.

• E2M - 전기 전자와 첨단 소재
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• 제10권1호
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• pp.26-32
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• 1997

The gate induced drain leakage(GIDL) current under the stress of worse case in -MOSFET's with ultrathin gate oxides has been measured and characterized. The GIDL current was shown that P-MOSFET's of the thicker gate oxide is smaller than that of the thinner gate oxide. It was the results that the this cur-rent is decreased with the increamental stress time at the same devices.It is analyzed that the formation components of GIDL current are both energy band to band tunneling at high gate-drain voltage and energy band to defect tunneling at low drain-gate voltage. The degradations of GIDL current was analyzed the mechanism of major role in the hot carriers trapping in gate oxide by on-state stress.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제50권10호
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• pp.532-535
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• 2001

The sputtering condition of Cr thin film was established in order to get Cr gate electrode having a vertical wall structure for Mo-tip FEA. In case of Mo-tip FEA which had a vertically-etched Cr gate electrode, the field enhancement factor, was relatively increased and so the field emission performance in terms of turn-on voltage, emission current and trans-conductance could be improved when compared with the devices having a tapered gate wall.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.230-231
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• 2012

This paper describes a gate driver that operates numerous semiconductor switch in the solide-state pulsed power modulator. the proposed gate driver is designed to receive both the isolated drive-power and the on/off pulse signals through the transformer. Moreover, the IGBT-switch can be quickly turned off by adding protection circuit. Therefore it protects the IGBT-switch from the arc condition that frequently occurs in high-voltage pulse application. To comprehend operating characteristic of each IGBT-switch in pulse output condition, the device consisting of a high efficiency soft-switching capacitor charger and two series stacking IGBT-switch is developed. Finally, the relability of the proposed gate driver and the device for its test are proved through PSpice simulation and experiments.