• Transactions on Electrical and Electronic Materials
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• v.13 no.4
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• pp.188-191
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• 2012

This paper introduces a new method regarding deuterium incorporation in the gate dielectric including deuterium implantation and post-annealing at the back-end-of-the process line. The control device and the deuterium furnace-annealed device were also prepared for comparison with the implanted device. It was observed that deuterium implantation at a light dose of $1{\times}10^{12}-1{\times}10^{14}/cm^2$ at 30 keV reduced hot-carrier injection (HCI) degradation and negative bias temperature instability (NBTI) within our device structure due to the reduction in oxide charge and interface trap. Deuterium implantation provides a possible solution to enhance the bulk and interface reliabilities of the gate oxide under the electrical stress.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.200-200
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• 2010

이 논문에서는 field-effect mobility를 향상시키기 위해 triple-layer (SiNx/SiO2/SiOxNy stack 구조)를 gate dielectric material 로 LTPS TFTs에 적용하였다. 이는 플라즈마 처리 기법과 적층구조의 효과적인 in-situ 공정을 이용하여 interface trap과 mobile charge를 낮추어 높은 이동도의 결과를 생각하고 실험하였다. 실험은 SiO2 gatedielectric과 triple-gate dielectric의 C-V curve를 1 MHz의 주파수에서 측정하였다. 또한 Transfer characteristics를 single SiO2 gatedielectric과 triple-gate dielectric of SiNx/SiO2/SiOxNy를 STA 장비를 이용해 측정하였다. 위의 측정을 통해 threshold voltage, mobility, subtheshold swing, driving current, ON/OFF current ratio를 비교 분석하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.3
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• pp.181-185
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• 2003

Influence of post gate oxidation anneal on Negative Bias Temperature Instability (NBTI) of PMOSFE has been investigated. At oxidation anneal temperature raised above 950$^{\circ}$C, a significant improvement of NBTI was observed which enables to reduce PMO V$\_$th/ shift occurred during a Bias Temperature (BT) stress. The high temperature anneal appears to suppress charge generations inside the gate oxide and near the silicon oxide interface during the BT stress. By measuring band-to-band tunneling currents and subthreshold slopes, reduction of oxide trapped charges and interface states at the high temperature oxidation anneal was confirmed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1988.10a
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• pp.79-81
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• 1988

The capacitance-voltage (C-V) characteristics of poly-Si gate MOS devices fabricated by Low-Pressure Chemical Vapor Deposition (LPCVD) system have been studied. In the case poly-Si gate, work function difference and surface state charge density was found lower than that of Al gate. This fact was identified from the C-V curves that flatband shift was shown small due to the hydrogen gas diffused into oxide in processing of alloy and the annealing effect in processing of poly-Si deposition.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.12 no.6
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• pp.304-310
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• 2002

Novel charge trap type memory devices with reoxidized oxynitride gate dielectrics made by NO annealing and reoxidation process of initial oxide on substrate have been fabricated using 0.35 $\mu \textrm{m}$ retrograde twin well CMOS process. The feasibility for application as NVSM memory device and characteristics of traps have been investigated. For the fabrication of gate dielectric, initial oxide layer was grown by wet oxidation at $800^{\circ}C$ and it was reoxidized by wet oxidation at $800^{\circ}C$ after NO annealing to form the nitride layer for charge trap region for 30 minutes at $850^{\circ}C$. The programming conditions are possible in 11 V, 500 $\mu \textrm{s}$ for program and -13 V, 1ms for erase operation. The maximum memory window is 2.28 V. The retention is over 20 years in program state and about 28 hours in erase state, and the endurance is over $3 \times 10^3$P/E cycles. The lateral distributions of interface trap density and memory trap density have been determined by the single junction charge pumping technique. The maximum interface trap density and memory trap density are $4.5 \times 10^{10} \textrm{cm}^2$ and $3.7\times 10^{18}/\textrm{cm}^3$ respectively. After $10^3$ P/E cycles, interlace trap density increases to $2.3\times 10^{12} \textrm{cm}^2$ but memory charges decreases.

• ETRI Journal
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• v.31 no.5
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• pp.604-606
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• 2009

The primary dose effects on an insulated gate bipolar transistor (IGBT) irradiated with a $^{60}Co$ gamma-ray source are found in both of the components of the threshold shifting due to oxide charge trapping in the MOS and the reduction of current gain in the bipolar transistor. In this letter, the IGBT macro-model incorporating irradiation is implemented, and the electrical characteristics are analyzed by SPICE simulation and experiments. In addition, the collector current characteristics as a function of gate emitter voltage, VGE, are compared with the model considering the radiation damage of different doses under positive biases.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.228-239
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• 2004

In this paper, an analytical model accounting for the quantum effects in MOSFETs has been developed to study the behaviour of $high-{\kappa}$ dielectrics and to calculate the threshold voltage of the device considering two dielectrics gate stack. The effect of variation in gate stack thickness and permittivity on surface potential, inversion layer charge density, threshold voltage, and $I_D-V_D$ characteristics have also been studied. This work aims at presenting a relation between the physical gate dielectric thickness, dielectric constant and substrate doping concentration to achieve targeted threshold voltage, together with minimizing the effect of gate tunneling current. The results so obtained are compared with the available simulated data and the other models available in the literature and show good agreement.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.7
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• pp.594-599
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• 2005

In this paper, we report the properties of Mo metal employed as PMOS gate electrode. Mo on $SiO_2$ was observed to be stable up to $900^{\circ}C$ by analyzing the Interface with XRD. C-V measurement was performed on the fabricated MOS capacitor with Mo Bate on $SiO_2$. The stability of EOT and work-function was verified by comparing the C-V curves measured before and after annealing at 600, 700, 800, and $900^{\circ}C$. C-V hysteresis curve was performed to identify the effect of fired charge. Gate-injection and substrate-injection of carrier were performed to study the characteristics of $Mo-SiO_2$ and $SiO_2-Si$ interface. Sheet resistance of Mo metal gate obtained from 4-point probe was less than $10\;\Omega\Box$ that was much lower than that of polysilicon.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.67-78
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• 1984

EAROM device is an n-channel MOS transistor with a control gate stack ed on the floating gate. On account of channel injection type, channel lengths are designed 4-8 $\mu$m and chinnel widths 5-14 $\mu$m. These devices which have fourstructures of different type control gate are designed by NMOS 5 $\mu$m design rule and fabricated by double polysilicon gate NMOS Process. Double ion implantation is applied to increase punchthrough voltage and gate-controlled channel breakdown voltage. The drain and gate voltage for programming was 13-17V and 20-25V, respectively. EPROM cell fabricated could be erased not by optical method but by electrical method. The result of charge retention test showed decrease in stored charges by 4% after 200 hours at 1$25^{\circ}C$.