• Journal of the Korean Institute of Telematics and Electronics
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• v.18 no.3
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• pp.25-34
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• 1981

Aluminum anodization method has been investigated for fabricating charge coupled device(CCD) with two-level aluminum gate structure. Al2O3 films were formed to a thickness of 400-500A, by anodizing aluminum with 30-35V of anode voltage for 2 hours using 2 % ammonium tartrate solution as an electrolyte. Breakdown voltage of these films were about 30 volts. Using above mentioned Al2O3 film as an insulator between two aluminum electrodes, CCD transversal low pass filter has been fabricated. CCD transversal low pass filter with 17 tap coefficients has shown 22 dB stop-band attenuation. The operating clock frequency range of the fabricated device was from 3 KHz to 100 KHz.

• Journal of the Korean Institute of Telematics and Electronics
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• v.22 no.3
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• pp.68-76
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• 1985

A charge-coupled device (CCD) area image sensor has been demonstrated with an experi-mental 16$\times$16 prototype. The prototype is a vertical frame transfer charge.coupled imager using two-phase gate electrode structures. In this device, ion-implanted barriers are used for two -phase CCD, and NMOS process has been adopted. The total imaging setup consisting of optical lens, clock generators, clock drivels, staircase signal generators, and oscilloscope is easily achieved with the aid of PROM . English alphabets are displayed on the oscilloscope screen using the total imaging set-up. We measure charge transfer inefficiency and dark current for the fabricated devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.1
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• Journal of Electrical Engineering and Technology
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• v.7 no.2
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• pp.236-239
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• 2012

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the $SiO_2$/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.161-165
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• 2023

This paper designed a voltage feedback driving circuit to compensate for the characteristic deviation of the Active Matrix Organic Light Emitting Diode driving Thin Film Transistor. This paper describes a stable and fast circuit by applying charge sharing and polar stabilization methods. A 12-inch Organic Light Emitting Diode with a Double Wide Ultra eXtended Graphics Array resolution creates a screen distortion problem for line parasitism, and charge sharing and polar stabilization structures were applied to solve the problem. By applying Charge Sharing, all data lines are shorted at the same time and quickly positioned as the average voltage to advance the compensated change time of the gate voltage in the next operation period. A buffer circuit and a current pass circuit were added to lower the Amplifier resistance connected to the line as a polar stabilization method. The advantage of suppressing the Ringing of the driving Thin Film Transistor can be obtained by increasing the stability. As a result, a circuit was designed to supply a stable current to the Organic Light Emitting Diode even if the characteristic deviation of the driving Thin Film Transistor occurs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.3
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• pp.6-13
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• 2000

Ultra-thin gate oxide was grown on nitrogen implanted silicon substrates. For nitrogen implantation, the energy was fixed at 25keV, but the dose was split into 5.0$\times$10$^{13}$ /c $m^{2}$ and 1.0$\times$10$^{14}$ /c $m^{2}$. The grown gate oxide thickness were 2nm, 3nm and 4nm. The oxidation time to grow 3nm was increased by 20% and 50% for the implanted wafers of 5.0$\times$10$^{13}$ /c $m^{2}$ and 1.0$\times$10$^{14}$ /c $m^{2}$ doses, respectively, when it was compared with control wafers which were not implanted by nitrogen. The value of charge-to-breakdown ( $Q_{BD}$ ) is decreased with increasing nitrogen doses. If an annealing process( $N_{2}$, 85$0^{\circ}C$, 60min.) is peformed after nitrogen implantation, $Q_{BD}$ is increased. It is indicated that nitrogen implantation damage affect gate oxide reliability and the damage can be removed by post-implantation annealing process.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.48 no.2
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• pp.86-90
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• 2011

The effects of cations are very important in field-effect transistors (FETs) type DNA sensors detecting the intrinsic negative charge between single-stranded DNA and double-stranded DNA without labeling, because the intrinsic negative charge of DNA is neutralized by cations in electrolyte solution. We consider the Debye length, which depends on the concentration of cations in solution, to detect DNA hybridization based on the intrinsic negative charge of DNA. The Debye length is longer in buffer solution with a lower concentration of NaCl and the intrinsic negative charge of DNA is more effective on the channel surface in longer Debye length solution. The shifts in the gate voltage by DNA hybridization with complementary target DNA are 21 mV in 1 mM NaCl buffer solution, 7.2 mV in 10 mM NaCl buffer solution, and 5.1 mV in 100 mM NaCl buffer solution. The sensitivity of FETs to detect DNA hybridization based on charge detection without labeling depends on the Debye length.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.40-49
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• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.1
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• pp.27-31
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• 2008

We have studied nonvolatile memory properties of MOSFETs with double-stacked Si nanoclusters in the oxide-gate stacks. We formed Si nanoclusters of a uniform size distribution on a 5 nm-thick tunneling oxide layer, followed by a 10 nm-thick intermediate oxide and a second layer of Si nanoclusters by using LPCVD system. We then investigated the memory characteristics of the MOSFET and observed that the charge retention time of a double-stacked Si nanocluster MOSFET was longer than that of a single-layer device. We also found that the double-stacked Si nanocluster MOSFET is suitable for use as a dual-bit memory.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.97-97
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• 2013

We present a comprehensive study on the integration of h-BN with silicon MOSFET. Temperature dependent mobility modeling is used to discern the effects of top-gate dielectric on carrier transport and identify limiting factors of the system. The result indicates that coulomb scattering and surface roughness scattering are the dominant scattering mechanisms for silicon MOSFETs at relatively low temperature. Interposing a layer of h-BN between $SiO_2$ and Si effectively weakens coulomb scattering by separating carriers in the silicon inversion layer from the charged centers as 2-dimensional h-BN is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure, thus leading to a significant improvement in mobility relative to undecorated system. Furthermore, the atomically planar surface of h-BN also suppresses surface roughness scattering in this Si MOSFET system, resulting in a monotonously increasing mobility curve along with gate voltage, which is different from the traditional one with a extremum in a certain voltage. Alternatively, high-k dielectrics can lead to enhanced transport properties through dielectric screening. Modeling indicates that we can achieve even higher mobility by using h-BN decorated $HfO_2$ as gate dielectric in silicon MOSFETs instead of h-BN decorated $SiO_2$.