• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.35-38
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• 2018

This paper describes a low-power MPPT interface for DC-type energy harvesting sources. The proposed circuit consists of an MPPT controller, a bias generator, and a voltage detector. The MPPT controller consists of an MPG (MPPT Pulse Generator) with a schmitt trigger, a logic gate operating according to energy type (light, heat), and a sample/hold circuit. The bias generator is designed by employing a beta multiplier structure, and the voltage detector is implemented using a bulk-driven comparator and a two-stage buffer. The proposed circuit is designed with $0.35{\mu}m$ CMOS process. The simulation results show that the designed circuit consumes less than 100nA of current at an input voltage of less than 3V and the maximum power efficiency is 99.7%. The chip area of the designed circuit is $1151{\mu}m{\times}940{\mu}m$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.71-78
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• 1994

We have developed GaAs power metal semiconductor field effect transistors (MESFETs) for 4.7V operation under 900 MHz using a low-high deped structures grown by molecular beam epitaxy (MBE). The fabricted MESFETs with a gate widty of 7.5 mm and a gate length of 1.0.mu.m show a saturated drain current (Idss) of 1.7A and an uniform transconductance (Gm) of around 600mS, for gate bias ranged from -2.4 V to 0.5 V. The gate-drain breakdown voltage is measured to be higher than 25 V. The measured rf characteristics of the MESFETs at a frequency of 900 MHz are the output power of 31.4 dBm and the power added efficiency of 63% at a drain bias of 4.7 V.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.204.1-204.1
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• 2015

We studied the electrical properties and gate bias stress (GBS) stability of thin film transistors (TFTs) with multi-stacked InZnO layers. The InZnO TFTs were fabricated via solution process and the In:Zn molar ratio was 1:1. As the number of InZnO layers was increased, the mobility and the subthreshold swing (S.S) were improved, and the threshold voltage of TFT was reduced. The TFT with three-layered InZnO showed high mobility of $21.2cm^2/Vs$ and S.S of 0.54 V/decade compared the single-layered InZnO TFT with $4.6cm^2/Vs$ and 0.71 V/decade. The three-layered InZnO TFTs were relatively unstable under negative bias stress (NBS), but showed good stability under positive bias stress (PBS).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.1-7
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• 2009

In this paper, a simple analytical model for deriving the threshold voltage of a short-channel intrinsic-body SDG SOI MOSFET is suggested. Using the iteration method, both Laplace equations in intrinsic silicon body and gate oxide are solved two-dimensionally. Obtained potential distributions in both regions are expressed in terms of fourth and fifth-order of the coordinate perpendicular to the silicon channel direction. Making use of them, the surface potential is obtained to derive the threshold voltage in a closed-form. Simulation results show the fairly accurate dependencies of the threshold voltage on the various device parameters and applied bias voltages.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.7
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• pp.580-583
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• 2009

This paper introduces a gate drive IC for power modules with shoot-through immunity. A new approach uses a bootstrap diode as a high-side voltage bias and a level shift function at the same time. Therefore, the gate drive circuit becomes a simple and low-cost without conventional level shift functions such as HVIC(High-Voltage IC), optocoupler and transformer. The proposed gate drive IC is designed and fabricated using the Dongbu-Hitek's 0.35um BD350BA process. It has been tested and verified with IGBT modules.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.8
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• pp.365-370
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• 2001

We have proposed and fabricated a new poly-Si TFT employing air-cavities at the edges of gate oxide in order to reduce the vertical electric field induced near the drain due to low dielectric constant of air. Air-cavity has been successfully fabricated by employing the wet etching of gate oxide and APCVD (Atmospheric pressure chemical vapor deposition) oxide deposition. Our experimental results show that the leakage current of the proposed TFT is considerably reduced by the factor of 10 and threshold voltage shift under high gate bias is also reduced because the carrier injection into gate insulator over the drain depletion region is suppressed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.81-82
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• 2009

This paper introduces a gate drive IC for power modules with shoot-through immunity. A new approach uses a bootstrap diode as a high-side voltage bias and a level shift function at the same time. Therefore, the gate drive circuit becomes a simple and low-cost without conventional level shift functions such as HVIC(High-Voltage IC), optocoupler and transformer. The proposed gate drive IC is designed and fabricated using the Dongbu-Hitek's 0.35um BD350BA process. It has been tested and verified with IGBT modules.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.4
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.121-126
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• 1996

In this paper an MMIC VCO which can be used in a double conversion TV tuner is designed, fabricated and measured. The VCO is designed using the small signal method and fabricated using ETRI GaAs MMIC foundry. The 3x200$\mu$m gate width MESFET with 1$\mu$m gate length is used for an active device and MIM capacitors, spiral inductors, thin film resitors are used as passive elements. The VCO has output power of 10.95dBm at 1955 MHz with 5V bias voltage and 4V tuning voltage. The oscillation frequency change form 1947 MHz to 1964 MHz is obtaine dby an external varactor diode connected to the gate with a tuning voltage from 0 V to 6V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.90-93
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• 1996

The conduction mechanisms of the off-current in low temperature ($\leq$600$^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT's) has been systematically studied. Especially, the temperature and bias dependence of the off-current between unpassivated and passivated poly-Si TFT's was investigated and compared. The off-current of unpassivated poly-Si TFT's is due to a resistive current at low gate and drain voltage, thermal emission current at high gate, low drain voltage, and field enhanced thermal emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation, it was observed that the off-currents were remarkably reduced by plasma-hydrogenation. It was also observed that the off-currents of the passivated poly-Si TFT's are more critically dependent on temperature rather than electric field.