JSTS:Journal of Semiconductor Technology and Science

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Introduction to Industrial Applications of Low Power Design Methodologies

  • Received : 2009.07.31
  • Published : 2009.12.30
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Abstract

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

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References

  1. S. G. Narendra and A. Chandrakasan, Leakage in nanometer CMOS technologies, New York: Springer-Verlag, 2005
  2. K. Roy, S. Mukhopadhyay, and H. Mahmoodi- Meimand, "Leakage current mechanisms and leakage reduction techniques in deep-submicronmeter CMOS circuits," IEEE, Vol.92, No.2, pp.305–327, Feb., 2003 https://doi.org/10.1109/JPROC.2002.808156
  3. L. T. Clark, M. Morrow, and W. Brown, 'Reverse-body bias and supply collapse for low effective standby power," IEEE Trans. Very Large Scale Integr. (VLSI), Vol.12, No.9, pp.947–956, Sep., 2004 https://doi.org/10.1109/TVLSI.2004.832930
  4. M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, Y. Hagihara, "Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes," IEEE J. Solid-State Circuits, Vol.41, No.4, pp.805–814, Apr., 2006 https://doi.org/10.1109/JSSC.2006.870796
  5. G. Gammie, A. Wang, M. Chau, S. Gururajarao, R. Pitts, F. Jumel et al., "A 45nm 3.5G baseband-and multimedia application processor using adaptive body-bias and ultra-low-power techniques,' in Proc. Int. Solid-State Circuits Conf., Feb., 2008, pp.258–259
  6. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "A 1-V power supply high-speed digital circuit technology with multiple threshold-voltage CMOS," IEEE J. Sold-State Circuits, Vol.30, No.8, pp.847–854, Aug., 1995 https://doi.org/10.1109/4.400426
  7. S. V. Kosonocky, M. Immediato, P. Cottrell, and T. Hook, "Enhanced multi-threshold (MTCMOS) circuits using variable well bias," in Proc. Int'l Symposium on Low Power Electronics and Design, Aug., 2001, pp.165–169 https://doi.org/10.1109/LPE.2001.945394
  8. H.-O. Kim, Y. Shin, H. Kim, and I. Eo, "Physical design methodology of power gating circuits for standard-cell-based design," in Proc. Design Automat. Conf., July, 2006, pp.109–113
  9. S. Borkar, T. Kamik, S. Narendra, J. Tscanz, A. Keshavarzi, and V. De, "Parameter variations and impact on circuits and microarchitecture," in Proc. Design Automat. Conf., June, 2003, pp.338–342
  10. B. Choi and Y. Shin, "Lookup table-based adaptive body biasing of multiple macros," in Proc. Int'l Symposium on Quality Electronic Design, March 2007, pp.533–538 https://doi.org/10.1109/ISQED.2007.98
  11. J.Y. Choi, H.-S. Won, Y. Shin, J. Seomun, and B. Choi, "Lookup table based adaptive body biasing of multiple macros," Korea patent 10-0817058-0000, Mar. 2008
  12. L. L. C. Hsu, G. Frankowsky, and O. Wienfurtner, "Dynamic DRAM refresh rate adjustment based on cell leakage monitoring," U.S. patent 6483764 B2, Nov., 2002
  13. T. Chen and S. Naffziger, "Comparison of adaptive body bias (ABB) and adaptive supply voltage (ASV) for improving delay and leakage under the presence of process variation," IEEE Trans. Very Large Scale Integr. (VLSI), Vol.11, No.5, pp.888–899, Oct., 2003 https://doi.org/10.1109/TVLSI.2003.817120
  14. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, "High-k/Metal-gate stack and its MOSFET characteristics," IEEE Electron Device Letters, Vol.25, No.6, pp.408–410, June, 2004
  15. R. Rao, A. Srivastava, D. Blaauw, and D. Sylbester, "Statistical analysis of subthreshold leakage current for VLSI circuits," IEEE Trans. Very Large Scale Integr. (VLSI), Vol.12, No.2, pp.131–139, Feb., 2004 https://doi.org/10.1109/TVLSI.2003.821549
  16. H. F. Jyu, S. Malik, S. Devadas, and K. Keutzer, "Statistical timing analysis of combinational circuits," IEEE Trans. Very Large Scale Integr. (VLSI), Vol.1, No.2, pp.126–137, June, 1993 https://doi.org/10.1109/92.238423
  17. J. Jeong, S. Paik, and Y. Shin, "Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation,' in Proc. Asia South Pacific Design Automat. Conf., Jan., 2008, pp.629–634
  18. L. Pileggi, H. Schmit, A. J. Strojwas, P. Gopalakrishnan, V. Kheterpal, A. Koorpaty, C. Patel, V. Rovner, and K. Y. Tong, "Exploring regular fabrics to optimize the performance cost trade-off," in Proc. Design Automat. Conf., June 2003, pp.782–787 https://doi.org/10.1145/775832.776031