• 대한전자공학회논문지TC
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• 제45권12호
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• pp.1-6
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• 2008

본 논문에서는 전력증폭기의 입력신호의 크기에 따라 CMOS class-E 전력증폭기의 게이트와 드레인의 바이어스 전압을 조절함으로써 낮은 출력전력에서도 80% 이상의 고효율 특성을 갖는 CMOS class-E 전력증폭기를 설계하였다. 입력신호의 포락선을 검파하여 전력증폭기의 바이어스 전압을 조절하는 방법을 이용하였고, 동작주파수는 2.14GHz, 출력전력은 22dBm에서 25dBm, 전력부가효율은 모든 입력전력레벨에서 80.15%에서 82.96%의 특성을 얻을 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
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• pp.122-122
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• 2008

Recently, Metal/Alumina/Silicon-Nitride/Silicon-Oxide/Silicon (MANOS) structures are one of the most attractive candidates to realize vertical scaling of high-density NAND flash memory [1]. However, as ANO layers are miniaturized, negative and positive bias temperature instability (NBTI/PBTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density increase, ${\Delta}D_{it}$, the gate leakage current, ${\Delta}I_G$. and the retention characteristics, in MONOS capacitors, becomes an important issue in terms of reliability. It is well known that tunnel oxide degradation is a result of the oxide and interfacial traps generation during FN (Fowler-Nordheim) stress [2]. Because the bias temperature stress causes an increase of both interfacial-traps and fixed oxide charge could be a factor, witch can degrade device reliability during the program and erase operation. However, few studies on NBTI/PBTI have been conducted on improving the reliability of MONOS devices. In this work, we investigate the effect of post-annealing gas on bias temperature instability (BTI), such as the flat band voltage shift, ${\Delta}V_{FB}$, the interfacial trap density shift, ${\Delta}I_G$ retention characteristics, and the gate leakage current characteristics of MANOS capacitors. MANOS samples annealed at $950^{\circ}C$ for 30 s by a rapid thermal process were treated via additional annealing in a furnace, using annealing gases $N_2$ and $N_2-H_2$ (2 % hydrogen and 98 % nitrogen mixture gases) at $450^{\circ}C$ for 30 min. MANOS samples annealed in $N_2-H_2$ ambient had the lowest flat band voltage shift, ${\Delta}V_{FB}$ = 1.09/0.63 V at the program/erase state, and the good retention characteristics, 123/84 mV/decade at the program/erase state more than the sample annealed at $N_2$ ambient.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2013년도 추계학술대회
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• pp.698-701
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• 2013

비대칭 이중게이트(double gate; DG) MOSFET의 문턱전압이하 스윙의 게이트 산화막 두께에 대한 변화를 고찰하였으며 이를 위하여 포아송방정식의 해석학적 전위분포를 구하였다. 비대칭 DGMOSFET 소자는 대칭적 구조를 갖는 DGMOSFET와 달리 4단자 소자로서 상단과 하단의 게이트 산화막 두께 및 인가전압을 달리 설정할 수 있다. 포아송방정식을 풀 때 전하분포함수에 가우시안 함수를 적용함으로써 보다 실험값에 가깝게 해석하였다. 비대칭 DGMOSFET의 문턱전압 이하 스윙을 상 하단 게이트 산화막 두께 변화에 따라 관찰한 결과, 게이트 산화막 두께에 따라 문턱전압이하 스윙은 크게 변화하는 것을 알 수 있었다. 특히 상 하단 게이트 산화막 두께가 증가할 때 문턱전압이하 스윙 값도 증가하였으며 상단 게이트 산화막 두께의 변화가 문턱전압이하 스윙 값에 더욱 큰 영향을 미치고 있다는 것을 알 수 있었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• 센서학회지
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• 제7권5호
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• pp.364-371
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• 1998

Field programmable gate array (FPGA)의 전압 프로그램 요소(voltage programmable link)로써 사용될 새로운 안티퓨즈를 제조하였다. 제조된 안티퓨즈는 Al/$BaTiO_3/SiO_2$/TiW-실리사이드 구조를 갖는다. 안티퓨즈의 프로그램 전압은 $BaTiO_3$의 증착 두께를 조절함으로써 정확하게 조절할 수 있었다. $BaTiO_3(120{\AA})$/$SiO_2(120{\AA})$의 안티퓨즈에서 TiW-실리사이드 전극에 (-)극성을 인가하여 측정된 프로그램 전압은 14.4 V였으며, on-저항은 $40-50{\Omega}$의 값을 갖는다. 안티퓨즈의 전류-전압 특성은 Frenkel-Poole 전도 기구를 따르고 있으며, 그 특성은 인가 전압의 극성에 따라 차이를 보였다. 이것은 Al/$BaTiO_3$계면과 TiW-silicide/$SiO_2$계면 특성이 다르기 때문이다.

• 한국정보통신학회논문지
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• 제7권4호
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• pp.743-749
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• 2003

본 논문에서는, cold-HEMT의 게이트에 핀치오프 전압보다 약간 낮은 전압을 가함으로써 게이트 손상문제로부터 자유로우며 부가적인 DC 측정을 필요로 하지 않는 새로운 HEMT 소신호 모델링 방법을 제시한다. 제시된 방법에 의해서 모델링된 회로의 S-파라미터 이론치는 49개의 동작 바이어스점에서 측정치와 62GHz까지 뛰어난 일치를 보였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1348-1351
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• 2007

We demonstrated that the threshold voltage shift owing to a gate-bias stress is originated from the trapped charges at the interface between semiconductor layer and dielectric layer, and such drawback can be settled by applying long-term delay time to the gate electrode.

• E2M - 전기 전자와 첨단 소재
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• 제11권10호
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• pp.94-99
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• 1998

Suitable replacement materials for ultrathin SiO2 in deeply scaled MOSFETs such as lattice polarizable films, which have much higherpermittivities than SiO2, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown, and hot carrier effect measurements were done on 190 layers of TiO2 which were deposited through the metal-organic chemical vapor deposition of titanium tetrakis-isopropoxide (TTIP). Measurements of the high and low frequency capacitance indicate that virtually no interface state are created during constant current injection stress. The increase in leakage upon electrical stress suggests that uncharged, near-interface states may be created in the TiO2 film near the SiO2 interfacial layer that allow a tunneling current component at low bias.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.867-872
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• 2016

We have investigated the channel mobility of AlGaN/GaN-on-Si recessed-metal-oxide-semiconductor-heterojunction field-effect transistors (recessed-MOS-HFET) with $SiO_2$ gate oxide. Both field-effect mobility and effective mobility for the recessed-MOS channel region were extracted as a function of the effective transverse electric field. The maximum field effect mobility was $380cm^2/V{\cdot}s$ near the threshold voltage. The effective channel mobility at the on-state bias condition was $115cm^2/V{\cdot}s$ at which the effective transverse electric field was 340 kV/cm. The influence of the recessed-MOS region on the overall channel mobility of AlGaN/GaN recessed-MOS-HFETs was also investigated.

• ETRI Journal
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• 제15권2호
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• pp.11-25
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• 1993

Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.