• Journal of the Semiconductor & Display Technology
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• v.18 no.1
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• pp.59-64
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• 2019

Recently, time synchronous has become important for satellite launch control facilities, multiple thermal power plants, and power system facilities. Information from time synchronous at each of these industrial sites requires time synchronization to control or monitor the system with correlation. In this paper, IRIG-B codes, which can be used for time synchronous, are used as specifications in IRIG standard 200-16. Signals from IRIG-B120 (Analog), IRIG-B000 (Digital), and one PPS are output from GPS receiver. Using the signal from IRIG-B120 (Analog), it passes through the signal from the analog amplifier and generates one PPS signal using the field-programmable gate array. The FPGA is used cyclone EPM570T100I5N. According to IEEE regulations, the error of one PPS is specified within 1us, but in this paper, the error is within 100ns. The output of the one PPS signal was then compared and tested against the one PPS signal on the GPS receiver to verify accuracy and reliability. In addition, the proposed time synchronous is simple to construct and structure, easy to implement, and provides high time precision compared to typical time synchronous. The output of the one PPS signals and IRIG-B000 signal will be used in many industry sectors.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.12
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• pp.5654-5668
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• 2018

Driven by security and real-time demands of Internet of Things (IoT), the timing of fog computing and edge computing have gradually come into place. Gateways bear more nearby computing, storage, analysis and as an intelligent broker of the whole computing lifecycle in between local devices and the remote cloud. In fog computing, the edge broker requires X-aware capabilities that combines software programmability, stream processing, hardware optimization and various connectivity to deal with such as security, data abstraction, network latency, service classification and workload allocation strategy. The prosperous of Field Programmable Gate Array (FPGA) pushes the possibility of gateway capabilities further landed. In this paper, we propose a software-defined gateway (SDG) scheme for fog computing paradigm termed as Fog Computing Zero-Knowledge Gateway that strengthens data protection and resilience merits designed for industrial internet of things or highly privacy concerned hybrid cloud scenarios. It is a proxy for fog nodes and able to integrate with existing commodity gateways. The contribution is that it converts Privacy-Enhancing Technologies rules into provable statements without knowing original sensitive data and guarantees privacy rules applied to the sensitive data before being propagated while preventing potential leakage threats. Some logical functions can be offloaded to any programmable micro-controller embedded to achieve higher computing efficiency.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.12
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• pp.4648-4663
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• 2020

This paper proposes the Lempel-Ziv 4(LZ4) compression accelerator optimized for scale-out servers in data centers. In order to reduce CPU loads caused by compression, we propose an accelerator solution and implement the accelerator on an Field Programmable Gate Array(FPGA) as heterogeneous computing. The LZ4 compression hardware accelerator is a fully pipelined architecture and applies 16 dictionaries to enhance the parallelism for high throughput compressor. Our hardware accelerator is based on the 20-stage pipeline and dictionary architecture, highly customized to LZ4 compression algorithm and parallel hardware implementation. Proposing dictionary architecture allows achieving high throughput by comparing input sequences in multiple dictionaries simultaneously compared to a single dictionary. The experimental results provide the high throughput with intensively optimized in the FPGA. Additionally, we compare our implementation to CPU implementation results of LZ4 to provide insights on FPGA-based data centers. The proposed accelerator achieves the compression throughput of 639MB/s with fine parallelism to be deployed into scale-out servers. This approach enables the low power Intel Atom processor to realize the Hadoop storage along with the compression accelerator.

• Journal of Information Processing Systems
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• v.17 no.6
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• pp.1097-1114
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• 2021

The primary objective of this work was to discover a solution for the survival of people in an emergency flood. The geographical information was obtained from remote sensing techniques. Through helpline numbers, people who are in need request support. Although, it cannot be ensured that all the people will acquire the facility. A proper link is required to communicate with people who are at risk in affected areas. Mobile sensor networks with field-programmable gate array (FPGA) self-configurable radios were deployed in damaged areas for communication. Ad-hoc networks do not have a centralized structure. All the mobile nodes deploy a temporary structure and they act as a base station. The mobile nodes are involved in searching the spectrum for channel utilization for better communication. FPGA-based techniques ensure seamless communication for the survivors. Timely help will increase the survival rate. The received signal strength is a vital factor for communication. Cognitive radio ensures channel utilization in an effective manner which results in better signal strength reception. Frequency band selection was carried out with the help of the GRA-MADM method. In this study, an analysis of signal strength for different mobile sensor nodes was performed. FPGA-based implementation showed enhanced outcomes compared to software-based algorithms.

• Nuclear Engineering and Technology
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• v.53 no.4
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• pp.1167-1175
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• 2021

The process of automation and monitoring in industrial control system involves the use of many types of sensors. A programmable logic controller plays an important role in the automation of the different processes in the power plant system. The major control units are boiler for temperature and pressure, turbine for speed of motor, generator for voltage, conveyer belt for fuel. The power plant units are controlled using microcontrollers and PLCs, but FPGA can be the feasible solution. The paper focused on the design and simulation of hardware chip to monitor boiler, turbine, generator and conveyer belt. The hardware chip of the plant is designed in Xilinx Vivado Simulator 17.4 software using VHDL programming. The methodology includes VHDL code design, simulation, verification and testing on Virtex-5 FPGA hardware. The system has four independent buzzers used to indicate the status of the boiler, generator, turbine motor and conveyer belt in on/off conditions respectively. The GSM is used to display corresponding message on the mobile to know the status of the device in on/off condition. The system is very much helpful for the industries working on plant automation with FPGA hardware integration.

• International Journal of Computer Science & Network Security
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• v.22 no.9
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• pp.414-426
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• 2022

Elliptic Curve Cryptography (ECC) is one of the finest cryptographic technique of recent time due to its lower key length and satisfactory performance with different hardware structures. In this paper, a High Throughput Multiplier architecture is introduced for Elliptic Cryptographic applications based on concurrent computations. With the aid of the concurrent computing approach, the High Throughput Concurrent Computation (HTCC) technology that was just presented improves the processing speed as well as the overall efficiency of the point-multiplier architecture. Here, first and second distinct group operation of point multiplier are combined together and synthesised concurrently. The synthesis of proposed HTCC technique is performed in Xilinx Virtex - 5 and Xilinx Virtex - 7 of Field-programmable gate array (FPGA) family. In terms of slices, flip flops, time delay, maximum frequency, and efficiency, the advantages of the proposed HTCC point multiplier architecture are outlined, and a comparison of these advantages with those of existing state-of-the-art point multiplier approaches is provided over GF(2¹⁶³), GF(2²³³) and GF(2²⁸³). The efficiency using proposed HTCC technique is enhanced by 30.22% and 75.31% for Xilinx Virtex-5 and by 25.13% and 47.75% for Xilinx Virtex-7 in comparison according to the LC design as well as the LL design, in their respective fashions. The experimental results for Virtex - 5 and Virtex - 7 over GF(2²³³) and GF(2²⁸³)are also very satisfactory.

• Journal of information and communication convergence engineering
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• v.20 no.3
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• pp.166-173
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• 2022

Recently, studies have been conducted on intelligent transportation systems (ITS) that provide safety and convenience to humans. Systems that compose the ITS adopt architectures that applied the cloud computing which consists of a high-performance general-purpose processor or graphics processing unit. However, an architecture that only used the cloud computing requires a high network bandwidth and consumes much power. Therefore, applying edge computing to ITS is essential for solving these problems. In this paper, we propose an edge artificial intelligence (AI) device based ITS. Edge AI which is applicable to various systems in ITS has been applied to license plate recognition. We implemented edge AI on a field-programmable gate array (FPGA). The accuracy of the edge AI for license plate recognition was 0.94. Finally, we synthesized the edge AI logic with Magnachip/Hynix 180nm CMOS technology and the power consumption measured using the Synopsys's design compiler tool was 482.583mW.

• Nuclear Engineering and Technology
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• v.55 no.8
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• pp.2873-2878
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• 2023

The purpose of this study is to perform radiation monitoring by acquiring gamma images and real-time optical images for ^99mTc vial source using charge couple device (CCD) cameras equipped with the proposed compact gamma camera. The compact gamma camera measures 86×65×78.5 mm³ and weighs 934 g. It is equipped with a metal 3D printed diverging collimator manufactured in a 45 field of view (FOV) to detect the location of the source. The circuit's system uses system-on-chip (SoC) and field-programmable-gate-array (FPGA) to establish a good connection between hardware and software. In detection modules, the photodetector (multi-pixel photon counters) is tiled at 8×8 to expand the activation area and improve sensitivity. The gadolinium aluminium gallium garnet (GAGG) measuring 0.5×0.5×3.5 mm³ was arranged in 38×38 arrays. Intrinsic and extrinsic performance tests such as energy spectrum, uniformity, and system sensitivity for other radioisotopes, and sensitivity evaluation at edges within FOV were conducted. The compact gamma camera can be mounted on unmanned equipment such as drones and robots that require miniaturization and light weight, so a wide range of applications in various fields are possible.

• Nuclear Engineering and Technology
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• v.55 no.8
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• pp.2952-2965
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• 2023

Advanced reactors, such as Small Modular Reactors or existing Nuclear Power Plants, often use Field Programmable Gate Array (FPGA) based controllers in new Instrumentation and Control (I&C) system architectures or as an alternative to existing analog-based I&C systems. Compared to CPU-based Programmable Logic Controllers (PLCs), FPGAs offer better overall performance. However, programming functions on FPGAs can be challenging due to the requirement for a hardware description language that does not explicitly support the operation of real numbers. This study aims to implement the Reactor Trip (RT) functions of the existing analog-based Reactor Protection System (RPS) using FPGAs. The RT equations for Overtemperature delta Temperature and Overpower delta Temperature involve dynamic compensators expressed with the Laplace transform variable, 's', which is not directly supported by FPGAs. To address this issue, the trip equations with the Laplace variable in the continuous-time domain are transformed to the discrete-time domain using the Z-transform. Additionally, a new operation based on a relative value for the equation range is introduced for the handling of real numbers in the RT functions. The proposed approach can be utilized for upgrading the existing analog-based RPS as well as digitalizing control systems in advanced reactor systems.

• Nuclear Engineering and Technology
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• v.55 no.2
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• pp.484-492
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• 2023

Time-to-digital converters (TDCs) based on the tapped delay line (TDL) architecture have been widely used in various applications requiring a precise time measurement. However, the poor uniformity of the propagation delays in the TDL implemented on FPGA leads to bubble error and large nonlinearity of the TDC. The purpose of this study was to develop an advanced TDC architecture capable of minimizing the bubble errors and improving the linearity. To remove the bubble errors, the decimated delay line (DDL) architecture was implemented on the UltraScale + FPGA; meanwhile, to improve the linearity of the TDC, a histogram uniformization (HU) and multi-chain TDL (MCT) methods were developed and implemented on the FPGA. The integral nonlinearities (INLs) and differential nonlinearities (DNLs) of the plain TDCs with the 'HU method' (HU TDC) and with 'both HU and MCT methods' (HU-MCT TDC) were measured and compared to those of the TDC with 'DDL alone' (plain TDC). The linearity of HU-MCT TDC were superior to those of the plain TDC and HU TDC. The experiment results indicated that HU-MCT TDC developed in this study was useful for improving the linearity of the TDC, which allowed for high timing resolution to be achieved.