• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.19 no.6
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• pp.79-85
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• 2019

Recently, small radar require the development of small millimeter wave radar with high distance resolution to disable the target's system with a single strike. Small millimeter wave radar with high distance resolution need to process large amounts of data in real time to acquire and track target. In this paper, we summarized the real-time data preprocessing method to process the large amount of data required for small millimeter wave radar. In addition, the digital IF(Intermediate Frequency) receiver, Window processing, and, DFT(Discrete Fourier Transform) functions presented by real-time data preprocessing are implemented using FPGA(Field Programmable Gate Array). Finally the implemented real-time data preprocessing module was applied to the signal processor for small millimeter wave radar and verified by performance test related to the real-time preprocessing function.

• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1240-1252
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• 1996

In this paper we propose a layout editor for the functional module generation in the Sea-of Gates(SOG) lay-out style. The proposed layout editor provides interactive was of designing a functional module to the designer so that the layout result is very satisfiable. Especially, the editor is independent on the shape of the basic cells in the gate array template, and provides semi-automatic layout methods as well as hand layout. It also has several special functions which are not able to find in other layout tools for the module generation, and hence the designer can generate modules very fast. The layout editors implemented in C language with X-win-dow Motif environment. When we compare our editor with the previous layout editor Seadali, the design time is reduced by a factor of two for several benchmark circuits.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.102-110
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• 2009

In this paper, we propose an object detection method for real-time in infrared (IR) images and PowerPC (PPC) and H/W design based on field programmable gate array (FPGA). An open H/W architecture has the advantages, such as easy transplantation of HW and S/W, support of compatibility and scalability for specification of current and previous versions, common module design using standardized design, and convenience of management and maintenance. Proposed background modeling for an open H/W architecture design decreases size of search area to construct a sparse block template of search area in IR images. We also apply to compensate for motion compensation when image moves in previous and current frames of IR sensor. Separation method of background and objects apply to adaptive values through time analysis of pixel intensity. Method of clutter reduction to appear near separated objects applies to median filter. Methods of background modeling, object detection, median filter, labeling, merge in the design embedded system execute in PFC processor. Based on experimental results, proposed method showed real-time object detection through global motion compensation and background modeling in the proposed embedded system.

• The Journal of the Acoustical Society of Korea
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• v.13 no.2E
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• pp.58-67
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• 1994

Hidden Markov Model (HMM)-based algorithms have been used successfully in many speech recognition systems, especially large vocabulary systems. Although general purpose processors can be employed for the system, they inevitably suffer from the computational complexity and enormous data. Therefore, it is essential for real-time speech recognition to develop specialized hardware to accelerate the recognition steps. This paper concerns with a real-time implementation of an isolated word recognition system based on HMM. The speech recognition system consists of a host computer (PC), a DSP board, and a prototype Viterbi scoring board. The DSP board extracts feature vectors of speech signal. The Viterbi scoring board has been implemented using three field-programmable gate array chips. It employs a hardware-efficient Viterbi scoring architecture and performs the Viterbi algorithm for HMM-based speech recognition. At the clock rate of 10 MHz, the system can update about 100,000 states within a single frame of 10ms.

• The Journal of the Acoustical Society of Korea
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• v.37 no.4
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• pp.215-222
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• 2018

This paper reports the development and performance evaluation of a backend system for real-time IVUS (Intravascular Ultrasound) imaging. The developed backend system was designed to minimize the amount of logic and memory usage by means of efficient LUTs (Look-up Tables), and it was implemented in a single FPGA (Field Programmable Gate Array) without using external memory. This makes it possible to implement the backend system that is less expensive, smaller, and lighter. The accuracy of the backend system implemented was evaluated by comparing the output of the FPGA with the result computed using a MATLAB program implemented in the same way as the VHDL (VHSIC Hardware Description Language) code. Based on the result of ex-vivo experiment using rabbit artery, the developed backend system was found to be suitable for real-time intravascular ultrasound imaging.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.12
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• pp.1033-1044
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• 2002

In this Paper, a new FRAM design technique utilizing grounded-plate PMOS-gate (GPPG) ferroelectric cell is proposed. A GPPG cell consists of a PMOS access transistor and a ferroelectric data storage capacitor. Its plate is grounded. The proposed architecture employs three novel methods for cell operation: 1) $V_{DD}$ -precharged bitline, 2) negative-voltage wordline technique and 3) negative-pulse restore. Because this configuration doesn't need the plate control circuitry, it can greatly increase the memory cell efficiency. In addition, differently from other reported common-plate cells, this scheme can supply a sufficient voltage of $V_{DD}$ to the ferroelectric capacitor during detecting and storing the polarization on the cell. Thus, there is no restriction on low voltage operation. Furthermore, by employing a compact column-path circuitry which activates only needed 8-bit data, this architecture can minimize the current consumption of the memory array. A 4- Mb FRAM circuit has been designed with 0.3-um, triple-well/1-polycide/2-metal technology, and the possibility of the realization of GPPG cell architecture has been confirmed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.10
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• pp.67-71
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• 2011

Existing face detection systems, which are used for digital door locks, digital cameras, video surveillance systems, and so on, are software-based implementation for relatively low level resolution images. Therefore, in this case, there are difficulties in detecting faces in a real-time fashion due to the increasing amount of operational processing as well as in allowing the requirements of face detections for HD(High Definition) resolutions. A hardware approach is necessary to efficiently find faces for HD images in real-time embedded systems. This paper proposes and implements a hardware architecture for an LBP(Local Binary Pattern) operation which is a time-consuming part as one of preprocessing steps for face detection. The hardware architecture proposed in this research has been implemented and tested with a FPGA(Field Programmable Gate Array) chip, and shown that the approach guarantees efficient face detection for HD images.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.73-79
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• 2007

In this paper the proposed transactor is customized and a generator which roles of automatically generating the transactor according to DUT(Design Under Test)'s input and output is implemented. The customized transactor is designed by rearranging the signals of depending on DUT and transactor protocol which consists of signals of the PCI interface between host computer and FPGA(Field Programmable Gate Array). The implemented automatic generator of transactor generates a Verilog code of transactor by adding DUT's information about input and output ports. Performance and normal working of the generated transactor has been verified by experiments with some verified hardware IPs. Also, an efficiency of the transactor has been verified by comparing with user's manually designed transactor and generated transactor. Moreover, the generator's flexibility has been verified for DUT's information of variable input and output. In case of using the implemented generator, a design time of transactor is reduced.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2373-2379
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• 2015

COMS(Communication, Ocean and Meteorological Satellite), the first Korean geostationary meteorological satellite, provides free meteorological information through HRIT/LRIT(High/Low Rate Information Transmission) service. This work presents the development of data receiver circuit that is essential to the implementation of a low-cost meteorological information receiver system. The data receiver circuit processes the data units according to the specification of physical layer and data link layer of HRIT/LRIT service. For this purpose, the circuit consists of a Viterbi decoder, a sync. word detector, a derandomizer, a Reed-Solomon decoder and so on. The circuit also supports PCI express interface to pass the information data on to the host PC. The circuit was implemented on an FPGA(field programmable gate array) and its function was verified through simulations and hardware implementation.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.4
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• pp.789-796
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• 2013

It is known that the detection of hopping signals without any information about hopping duration and hopping frequency is rather difficult. This paper considers the blind detection of hopping signal's information such as hopping duration and hopping frequency from the sampled wideband signals. In order to find hopping information from the wideband signals, multiple narrow-band filters are required in general, which leads to huge implementation complexity. Instead, this paper employs the polyphase DFT(discrete Fourier transform) filterbank to reduce the implementation complexity. This paper propose hopping signal detection algorithm from the polyphase DFT filterbank output. Specifically, based on the binary image processing, the proposed algorithm is developed to decrease the memory size and H/W complexity. The performance of the proposed algorithm is evaluated through the computer simulation and FPGA (field programmable gate array) implementation.