• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.33 no.10
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• pp.93-97
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• 2005

We have developed the FDSS (Fine Digital Sun Sensor) for the space technology of the STSAT-2 (Seience & Technology Satellite 2). The FDSS is firstly developed by using CMOS image sensor(CIS) in South Korea. The FDSS consists of the optics part, FPGA(Field Programable Gate Array) part, and MCU(Micro controller unit)part. This paper will focus on the optical characteristics of the optics part and describe the configuration of FDSS with the design of aperture. We also analyze the characteristic of optics about the pixel of the CMOS image sensor.

• Proceedings of the Korea Society of Information Technology Applications Conference
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• 2005.11a
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• pp.285-288
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• 2005

We propose a novel programmable miniature vision module based on a custom designed analog VLSI (aVLSI) chip. The vision module consists of the optical flow vision sensor embedded with commercial off-the-shelves digital hardware; in our case is the Intel XScale PXA270 processor enforced with a programmable gate array device. The aVLSI sensor provides gray-scale imager data as well as smooth optical flow estimates, thus each pixel gives a triplet of information that can be continuously read out as three independent images. The particular computational architecture of the custom designed sensor, which is fully parallel and also analog, allows for efficient real-time estimations of the smooth optical flow. The Intel XScale PXA270 controls the sensor read-out and furthermore allows, together with the programmable gate array, for additional higher level processing of the intensity image and optical flow data. It also provides the necessary standard interface such that the module can be easily programmed and integrated into different vision systems, or even form a complete stand-alone vision system itself. The low power consumption, small size and flexible interface of the proposed vision module suggests that it could be particularly well suited as a vision system in an autonomous robotics platform and especially well suited for educational projects in the robotic sciences.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.28 no.2
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• pp.287-293
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• 2018

Field Programmable Gate Array (FPGA) is widely used in a variety of fields because of its ability to be programmed as desired. However, when an externally implemented program is loaded on FPGA in the form of a bitstream, there is a possibility that hardware Trojans which cause malfunctions or leak information may be included. For this reason, bitstream reverse engineering is essential, and therefore related research has been conducted, such as BIL. In this paper, we analyze the BIL bitstream reverse engineering tool, which is the most representative algorithm, regarding its performance and limitations.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of Korea Multimedia Society
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• v.11 no.10
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• pp.1460-1470
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• 2008

As the performance of recent mobile systems increases, a vector graphic has been implemented to represent various types of dynamic menus, mails, and two-dimensional maps. This paper proposes a hardware accelerator for open vector graphics (OpenVG), which is widely used for two-dimensional vector graphics. We analyze the specifications of an OpenVG and divide the OpenVG into several functions suitable for hardware implementation. The proposed hardware accelerator is implemented on a field programmable gate array (FPGA) board using hardware description language (HDL) and is about four times faster than an Alex processor.

• Journal of the Korea Society of Computer and Information
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• v.7 no.4
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.142-146
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• 2012

Today, the demand for high-speed data communication and mobile communication has exploded. Thus, there is a growing need for optical communication systems that convert large volumes of data to optical signals and that accommodate and transmit the signals across long distances. Digital optical communication with these characteristics consists of a master unit (MU) and a slave unit (SU). However, the digital optical units that are currently commercialized or being developed transmit data without compression. Thus, digital optical communication using these units is restricted by the quantity of optical frames when adding diversity or operating with various combinations of CDMA, WCDMA, WiBro, GSM, LTE, and other mobile communication technologies. This paper suggests the application of a data compression algorithm to a digital signal processor (DSP) chip as a field programmable gate array (FPGA) and a complex programmable logic device (CPLD) of a digital optical unit to add separate optical waves or to transmit complex data without specific changes in design of the optical frame.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.5
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• pp.117-126
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• 1989

In this paper, a new placement algorithm for gate array lay out design is proposed. The proposed algorithm can treat the variable-sized macrocells and by considering the I/Q pad locations, the routing between I/Q pads and the internal region of a chip can be automated effectively. The algorithm is composed of 3 parts. which are initial partitioning, initial placement and placement improvement. In the initial placement phase, a given circuit is partitioned into 5 sub-circuits, by clustering method with considers connectivities of cells not only with I/Q pads but also with related partitioned groups is used repeatedly to assign a unique position to each cell. In the placement improvement phase, the concept of probabilistic wiring density is introduced, and cell moving algorithm is proposed to make the density in a chip even.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.11C
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• pp.1171-1177
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• 2002

In this paper, we proposed a high speed IP(Internet Protocol) packet forwarding engine of ATM(Asynchronous Transfer Mode) based label edge routers for POS(Packet over SONET) interface. The forwarding engine uses TCAM(Ternary Content Addressable Memory) for high performance lookup processing of the packet received from POS interface. We have accomplished high speed IP packet forwarding in hardware by implementing the functions of high speed IP header Processing and lookup control into FPGA(Field Programmable Gate Array). The proposed forwarding engine has the functions of label edge routers as the lookup controller supports MPLS(Multiprotocol Label Switching) packet processing functionality.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.