• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.367-372
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• 1999

We have investigated the effects of electrical stress on poly-Si TFTs with different hydrogen passivation conditions. The amounts of threshod voltage shift of hydrogen passivated poly-Si TFTs are much larger than those of as-fabricated devices both under the gate only and the gate and drain bias stressing. Also, we have quantitatively analyzed the degradation phenomena by analytical method. We have suggested that the electron trapping in the gate dielectric is the dominant degradation mechanism in only gate bias stressed poly-Si TFT while the creation of defects in the channel region and $poly-Si/SiO_2$ interface is prevalent in gate and drain bias stressed device.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.38 no.6
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.10
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• pp.71-78
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• 1994

We have developed GaAs power metal semiconductor field effect transistors (MESFETs) for 4.7V operation under 900 MHz using a low-high deped structures grown by molecular beam epitaxy (MBE). The fabricted MESFETs with a gate widty of 7.5 mm and a gate length of 1.0.mu.m show a saturated drain current (Idss) of 1.7A and an uniform transconductance (Gm) of around 600mS, for gate bias ranged from -2.4 V to 0.5 V. The gate-drain breakdown voltage is measured to be higher than 25 V. The measured rf characteristics of the MESFETs at a frequency of 900 MHz are the output power of 31.4 dBm and the power added efficiency of 63% at a drain bias of 4.7 V.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.10
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• pp.918-923
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• 1998

Poly-silicon thin film transistors were fabricated on quartz substrates by high temperature processes. Electrical characteristics were measured and compared for 3 transistor structures of Standard Inverted Gate(SIG), Lightly Doped Drain(LDD), and Dual Gate(DG). Leakage currents of DG and LDD TFT's were smaller that od SIG transistor, while ON-current of LDD transistor is much smaller than that of SIG and DG transistors. Temperature dependence of the leakage currents showed that SIG and DG TFT's had thermal generation current at small drian bias and Frenkel-Poole emission current at hight gate and drain biases, respectively. In case of LDD transistor, thermal generation was the dominant mechanism of leakage current at all bias conditions. It was found that the leakage current was closely related to the reduction of the electric field in the drain depletion region.

• Proceedings of the KIEE Conference
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• 1988.11a
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.4
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• pp.59-64
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• 2016

In this paper, a 10W GaN MMIC was designed and fabricated using the Ku-band SSPA module. For Design and fabrication of the SSPA module using Rogers(RO4003C) substrate was used for Branch-line structure. SSPA modules on budget Divider/Combiner was designed and fabricated less than the maximum insertion loss - 0.7dB. In addition, because it must be applied to the structural nature of GaN MMIC Gate Bias-Drain Bias circuit was implemented to apply the Gate-Drain sequential circuit, implemented the RF Power Detect, Temperature Detect, HPA On/Off function. Design and fabrication Ku-band SSPA Module got the measurement results that satisfy a maximum output of 15.6W, Gain 45.7dB, 19.0% efficiency.

• Advances in nano research
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• v.15 no.3
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• pp.263-275
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• 2023

The electron transport properties of Y-type zigzag branched carbon nanotubes (CNTs) are of great significance for micro and nano carbon-based electronic devices and their interconnection. Based on the semi-empirical method combining tight-binding density functional theory and non-equilibrium Green's function, the electron transport properties between the branches of Y-type zigzag branched CNT are studied. The results show that the drain-source current of semiconducting Y-type zigzag branched CNT (8, 0)-(4, 0)-(4, 0) is cut-off and not affected by the gate voltage in a bias voltage range [-0.5 V, 0.5 V]. The current presents a nonlinear change in a bias voltage range [-1.5 V, -0.5 V] and [0.5 V, 1.5 V]. The tangent slope of the current-voltage curve can be changed by the gate voltage to realize the regulation of the current. The regulation effect under negative bias voltage is more significant. For the larger diameter semiconducting Y-type zigzag branched CNT (10, 0)-(5, 0)-(5, 0), only the value of drain-source current increases due to the larger diameter. For metallic Y-type zigzag branched CNT (12, 0)-(6, 0)-(6, 0), the drain-source current presents a linear change in a bias voltage range [-1.5 V, 1.5 V] and is symmetrical about (0, 0). The slope of current-voltage line can be changed by the gate voltage to realize the regulation of the current. For three kinds of Y-type zigzag branched CNT with different diameters and different conductivity, the current-voltage curve trend changes from decline to rise when the branch of drain-source is exchanged. The current regulation effect of semiconducting Y-type zigzag branched CNT under negative bias voltage is also more significant.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.3
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• pp.145-152
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• 2003

Electrical gate and drain characteristics of double heterostructure InAlAs/InGaAs pseudomorphic HEMTs have been investigated under sub-bandgap photonic excitation ($hv). Drain $(V_{DS})-,{\;}gate($V_{DS})-$, and optical power($P_{opt}$)-dependent variation of the abnormal gate leakage current and associated physical mechanisms in the PHEMTs have been characterized. Peak gate voltage ($V_{GS,P}$) and the onset voltage for the impact ionization ($V_{GS.II}$) have been extracted and empirical model for their dependence on the $V_{DS}$ and $P_{opt} have been proposed. Anomalous gate and drain current, both under dark and under sub-bandgap photonic excitation, have been modeled as a parallel connection of high performance PHEMT with a poor satellite FET as a parasitic channel. Sub-bandgap photonic characterization, as a function of the optical power with $h\nu=0.799eV$, has been comparatively combined with those under dark condition for characterizing the bell-shaped negative humps in the gate current and subthreshold drain leakage under a large drain bias.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.7
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• pp.278-284
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• 1986

Double-diffused metal oxide power semiconductor field effect transistors are used extensively in recent years in various circuit applications. The temperature variation of the drain current at a fixed bias shows both positive and negative resistance characteristics depending on the gate threshold voltage and gate-to source bias votage. In this paper, the decision method of the gate crossover voltage by the temperature variation and a new method to determine the gate threshold voltage graphecally are presented.