• Proceedings of the Korean Vacuum Society Conference
• /
• 2016.02a
• /
• pp.267.1-267.1
• /
• 2016

본 연구에서는 nematic 액정의 종류 중 하나인 5CB (4-Cyano-4'-pentylbiphenyl) 물질을 박막 트랜지스터 (TFT)의 passivation 층으로 사용했을 때 그 전기적 특성향상을 확인하였다. RF-magnetron sputtering법으로 증착된 비정질 InGaZnO 박막을 활성층으로 사용한 TFT를 제작하여 그 활성층 위에 drop형식으로 passivation 하였다. 그 결과, drain current (I_DS)가 약 10배 정도 증가하고, linear region(V_D=0.5V)에서 mobility와 subthreshold slope(SS)이 각각 6.7에서 12.2, 0.3에서 0.2로 향상되는 것이 보였다. 이것은 gate bias가 인가되었을 때 freedericksz 전이를 통한 액정의 배향과 이때 형성된 dipole 형성에 의한 것으로 보이며, 이러한 LC의 배향은 편광현미경을 통하여 표면과 수직으로 배향한다는 사실을 확인 할 수 있었고 이 LC-passivation된 a-IGZO TFT의 전기적 특성의 향상에 대한 mechanism을 제시하였다. 그리고 배향한 LC가 가지는 dipole에 의해 bias stress 상황에서 독특한 electron trapping과 recovery의 증폭효과가 나타났다. V_G=+20V의 positive gate bias stress를 1000s동안 가했을 때, passivation되지 않은 a-IGZO TFT의 경우 +4V의 threshold voltage shift(${\Delta}V$_TH)가 발생되었고, 바로 -20V의 negative gate bias를 30s간 가해주었을 때 -2.5V의 ${\Delta}V$_TH가 발생하였다. 반면 LC-passivation된 a-IGZO TFT의 경우 각각 +5V와 -4V의 ${\Delta}V$_TH로 더 큰 변화를 가져왔다. 이러한 LC에 의한 electron trapping/recovery 증폭효과에 대한 model을 제시하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.6
• /
• pp.1-6
• /
• 2010

We present simulation results on DC characteristics of AlGaN/GaN HEMT having stair-type gate electrodes, in comparison with those of the conventional single gate AlGaN/GaN HEMTs and field-plate enhanced AlGaN/GaN HEMTs. In order to reduce the internal electric field near the gate electrode of conventional HEMT and thereby to increase their DC characteristics, we applied three-layered stacking electrode schemes to the standard AlGaN/GaN HEMT structure. As a result, we found that the internal electric field was decreased by 70% at the same drain bias condition and the transconductance (gm) was improved by 11.4% for the proposed stair-type gate AlGaN/GaN HEMT, compared with those of the conventional single gate and field-plate enhanced AlGaN/GaN HEMTs.

• Korean Chemical Engineering Research
• /
• v.60 no.2
• /
• pp.313-319
• /
• 2022

AlGaN/GaN based HfO₂ MOSHEMT (metal oxide semiconductor high electron transistor) with different gate recess depth was simulate to demonstrate a successful normally-off operation of the transistor. Three types of the HEMT structures including a conventional HEMT, a gate-recessed HEMT with 3 nm thick AlGaN layer, and MIS-HEMT without AlGaN layer in the gate region. The conventional HEMT showed a normally-on characteristics with a drain current of 0.35 A at V_G = 0 V and V_DS = 15 V. The recessed HEMT with 3 nm AlGaN layer exhibited a decreased drain current of 0.15 A under the same bias condition due to the decrease of electron concentration in 2DEG (2-dimensional electron gas) channel. For the last HEMT structure, distinctive normally- off behavior of the transistor was observed, and the turn-on voltage was shifted to 0 V.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.12
• /
• pp.27-34
• /
• 2004

The study on the RF substrate circuit is necessary to model RF output characteristics of deep submicron MOSFETs below 0.2$\mum$ gate length that have bun commercialized by the recent development of Si submicron process. In this paper, direct extraction methods are developed to apply for a simple substrate resistance model as well as another substrate model with connecting resistance and capacitance in parallel. Using these extraction methods, better agreement with measured Y22-parameter up to 30 GHz is achieved for 0.15$\mum$ CMOS device by using the parallel RC substrate model rather than the simple resistance one, demonstrating the RF accuracy of the parallel model and extraction technique. Using this model, bias and gate length dependent curves of substrate parameters in the RF region are obtained by increasing drain voltage of 0 to 1.2V at deep submicron devices with various gate lengths of 0.11 to 0.5㎛ These new extraction data will greatly contribute to developing a scalable RF nonlinear substrate model.

• Journal of IKEEE
• /
• v.3 no.2 s.5
• /
• pp.226-235
• /
• 1999

To investigate SPICE noise model and the behavior of its parameters, 1/f noise of NMOS devices fabricated by BiCMOS process is measured and compared to the various noise models and measured results. For the long channel devices, bias dependence of the drain current noise power spectral density $S_{Id}$ of NMOS is similar to the previous results. Equivalent gate noise power spectral density $S_{Vg}$ shows weak dependence on the gate and drain voltages in long channel NMOS as the previous results. However, it is shown that most of published noise models are difficult to apply to short channel devices. Therefore, in this study, with comparison of our experimental results, we have tried to find the model of 1/f noise, appropriate for our NMOS device fabricated by BiCMOS process.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.3
• /
• pp.107-116
• /
• 1996

Recently, the flash memory has been abstracting great attention in the semiconductor market in the world because of its potential applications as mass storage devices. One of the most significant barriers to the scalling-down of the stacked-gate devices such as EPROM's and flash EEPROM's is the large subthreshold leakage in the unselected cells connected with the bit line of a selected cell in the array during programming. The large subthreshold leakge is majorly due to the capacitive coupling between the floating gates of the unselectd cells and the bit line of selected cell. In this paper, a new programming method to redcue significantly the drain turn-on leakage in the unselected cells during programming has been studied, where a little positive voltage (0.25-0.75V) is applied to the soruce during programming unlike the conventional programming method in which the source is grounded. The resutls of the PISCES simulations and the electrical measurements for the standard EPROM with 0.35.mu.m effective channel length and 1.0.mu.m effective channel width show that the subthreshold leakage in the unselectd cells is significantly large when the source is grounded, whereas it is negligibly small when the source is biased ot a little positive voltage during programming. On the other hadn, the positive bias on the source is found to have little effects on the programming speed of the EPROM.

• Journal of information and communication convergence engineering
• /
• v.5 no.2
• /
• pp.116-120
• /
• 2007

In this paper, the image sensor using the a-Si:H TFT is proposed. The optimum amorphous silicon thin film is deposited using plasma enhanced chemical vapor deposition (PECVD). TFT and photodiode both with the thin film are fabricated and form image sensor. The photodiode shows that $I_{dark}\;is\;{\sim}10^{-13}\;A,\;I_{photo}\;is\;{\sim}10^{-9}\;A\;and\;I_{photo}/I_{dark}\;is\;{\sim}10^4$, respectively. In the case of a-Si:H TFT, it indicates that $I_{on}/I_{off}\;is\;10^6$, the drain current is a few ${\mu}A\;and\;V_{th}\;is\;2{\sim}4$ volts. For the analysis on the fabricated image sensor, the reverse bias of -5 volts in ITO of photodiode and $70 {\mu}sec$ pulse in the gate of TFT are applied. The image sensor with good property was conformed through the measured photo/dark current.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2007.08b
• /
• pp.1301-1304
• /
• 2007

We have investigated degradation of short channel n-type poly-Si TFTs with LDD under high gate and drain voltage stress due to self-heating. We have found that the threshold voltage of short channel TFT is shifted to negative direction on the selfheating stress, whereas the threshold voltage of long channel is moved to positive direction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2010.06a
• /
• pp.345-345
• /
• 2010

1T-DRAM cell with solid phase (SPC) crystallized poly-Si thin film transistor was fabricated and electrical characteristics were evaluated. The fabricated device showed kink effect by negative back bias. Kink current is due to the floating body effect and it can be used to memory operation. Current difference between "1" state and "0" state was defined and the memory properties can be improved by using gate induced drain leakage (GIDL) current.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2001.05a
• /
• pp.321-324
• /
• 2001

The metal-oxide-semiconductor field-effect transistor(MOSFET) has undergone many changes in the last decade in response to the constant demand for increased speed, decreased power, and increased packing density. This paper has compared Micro-Tec with ISE-TCAD. This paper investigates LDD MOSFET using two simulators. Bias condition is applied to the devices with gate lengths 180nm. We have presented MOSF ET's characteristics such as I-V characteristic, electric field. and compared with Micro-Tec and ISE-TCAD.