• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.7
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• pp.594-599
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• 2007

[ $CulnS_2$ ] thin films were synthesized by sulfurization of Cu/In Stacked elemental layer deposited onto glass Substrates by vacuum furnace annealing at temperature $200^{\circ}C$. And structural and electrical properties were measured in order to certify optimum conditions for growth of the ternary compound semiconductor $CuInS_2$ thin films with non-stoichiometry composition. $CuInS_2$ thin film was well made at the annealed $200^{\circ}C$ of SLG/Cu/In/S stacked elemental layer which was prepared by thermal evaporator, and chemical composition of the thin film was analyzed nearly as the proportion of 1 : 1 : 2. Physical properties of the thin film were investigated at various fabrication conditions substrate temperature, annealing and temperature, annealing time by XRD, FE-SEM and Hall measurement system. The compositional deviations from the ideal chemical formula for $200^{\circ}C$ material can be conveniently described by non-molecularity$({\Delta}x=[Cu/In]-1)$ and non-stoichiometry $({\Delta}y=[{2S/(Cu+3In)}-1])$. The variation of ${\Delta}x$ would lead to the formation of equal number of donor and accepters and the films would behave like a compensated material. The ${\Delta}y$ parameter is related to the electronic defects and would determine the type of the majority charge carriers. Films with ${\Delta}y>0$ would behave as p-type material while ${\Delta}y<0$ would show n-type conductivity. At the sane time, carrier concentration, hall mobility and resistivity of the thin films was $9.10568{\times}10^{17}cm^{-3},\;312.502cm^2/V{\cdot}s\;and\;2.36{\times}10^{-2}\;{\Omega}{\cdot}cm$, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.171-171
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• 2010

GaN 기반 Light emitting diodes(LEDs)의 p-type doping layer는 일반적으로 hole을 발생시키는 acceptor로 Mg이 사용하되고 있다. 보통 Mg이 도핑된 p-type GaN은 >$1\;{\Omega}{\cdot}cm$의 저항이 존재하는데 그 이유는 Mg의 열적 이온화를 위한 activation 에너지가 높아서 상온에서 valence band의 hole concentration는 전체 억셉터 농도의 1%가 되지 않기 ��문이다. 본 논문에서는 높은 hole 농도를 얻기 위해서 metalorganic chemical-vapor deposition (MOCVD)를 장비를 사용하여 사파이어 기판의 misorientation-angle에 따른 p-type a-plane(11-20) GaN 특성을 분석하였다. misorientation-angle은 c축 방향으로 $+0.15^{\circ}$, $-0.15^{\circ}$, $-0.2^{\circ}$, $-0.4^{\circ}$ off된 r-plane(1-102) 사파이어 기판 을 사용하였다. p-type 도핑물질로 bis-magnesium (Cp2Mg) 소스를 사용하였고 성장 과정중 발생하는 hydrogen passivation으로 인한 Mg-H complexes현상을 해결하기위해 conventional furnace annealing (CFA)와 rapid thermal annealing (RTA)를 이용하여 열처리 공정을 진행하였다. 열처리 공정은 Air와 N2 분위기에서 $650^{\circ}C$에서 $900^{\circ}C$ 사이의 다양한 온도에서 수행하였고 Hall 측정을 위해 Ni을 전극 물질로 사용하였다. 상온에서 Accent HL5500IU Hall system을 사용하여 hole concentration, mobility, specific resistance을 측정하였다. 열처리 공정 후 Hall측정 결과 $+0.15^{\circ}$, $-0.15^{\circ}$, $-0.2^{\circ}$, $-0.4^{\circ}$ off된 각 샘플들은 온도, 시간, 분위기에 따라 hole concentration ($7.4{\times}10^{16}cm^{-3}{\sim}6{\times}10^{17}cm^{-3}$), mobility(${\mu}h=\;1.72\;cm^2/V-s\;{\sim}15.2\;cm^2/V-s$), specific resistance(4.971 ohm-cm ~8.924 ohm-cm) 가 변화됨을 확인 할 수 있었다. 또한 광학적 특성을 분석하기 위해 Photoluminescence (PL)을 측정하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.91-91
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• 2010

현재 나노크기의 나노소자에 대한 관심과 연구가 활발히 진행 중에 있고, 나노소자 제작을 위한 나노구조체 연구에도 탄력을 받고 있다. 나노구조체 연구 중에서도 탄소나노튜브(CNT)와 실리콘이 많이 연구되고 있으나 CNT의 경우 금속과 반도체 등 전기적 특성이 혼재되어 분리기술이 필요하며, 실리콘 기반의 나노구조체들은 공기 중에 노출되었을 경우 자연 산화막 생성에 대한 문제점들이 대두되고 있다. 이러한 기존 나노구조체들의 문제점들을 극복하기 위해 산화물 계열의($InO_3$, ZnO와 $SnO_2$ 등) 나노구조체들이 화학, 광학 및 생화학 센서등의 다양한 응용 연구들이 진행되고 있다. 본 연구에서는 thermal evaporation법으로 tube furnace 장비를 이용하여 온도($500{\sim}900^{\circ}C$)변화에 따른 ZnO nanorod를 성장시켰다. 성장된 ZnO nanorod의 구조적 특성을 확인하기 위하여 전계방출주사전자현미경(SEM)을 측정한 결과 ZnO nanorod들은 직경 50~80nm, 길이는 400~1000nm 이상까지 다양한 직경과 길이를 가지고 성장되었으며 $800^{\circ}C$ 에서 성장된 ZnO nanorod가 가장 곧고 이상적인 nanorod의 형태를 이루는 것을 확인할 수 있었다. Nanorod는 온도가 높아질수록 nanowire로 성장됨에 따라 본 연구에서 $800^{\circ}C$ 에서는 nanorod형태를 이루고 있으나 $900^{\circ}C$에서부터 nanowire의 형태로 성장되었다. 또한 성장된 ZnO nanorod들의 X-선 회절패턴(XRD)을 측정 결과 ZnO의 (002) 우선 배양성 때문에 성장된 nanorod 또한 (002) 방향으로 성장되었음을 확인하였다. 이 연구를 통하여 온도를 조절함으로서 ZnO nanorod의 성장제어가 가능함을 확인하였고, 특성 분석을 통하여 발광소자, Solar Cell로의 응용가능성을 확인하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.240.2-240.2
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• 2013

The device scale of flash memory was confronted with quantum mechanical limitation. The next generation memory device will be required a break-through for the device scaling problem. Especially, graphene is one of important materials to overcome scaling and operation problem for the memory device, because ofthe high carrier mobility, the mechanicalflexibility, the one atomic layer thick and versatile chemistry. We demonstrate the hybrid memory consisted with the metal-oxide quantum dots and the mono-layered graphene which was transferred to $SiO_2$ (5 nm)/Si substrate. The 5-nm thick secondary $SiO_2$ layer was deposited on the mono-layered graphene by using ultra-high vacuum sputtering system which base pressure is about $1{\times}10^{-10}$ Torr. The $In_2O_3$ quantum dots were distributed on the secondary $SiO_2$2 layer after chemical reaction between deposited In layer and polyamic acid layer through soft baking at $125^{\circ}C$ for 30 min and curing process at $400^{\circ}C$ for 1 hr by using the furnace in $N_2$ ambient. The memory devices with the $In_2O_3$ quantum dots on graphene monolayer between $SiO_2$ thin films have demonstrated and evaluated for the application of next generation nonvolatile memory device. We will discuss the electrical properties to understating memory effect related with quantum mechanical transport between the $In_2O_3$ quantum dots and the Fermi level of graphene layer.

• Journal of the Korean Vacuum Society
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• v.22 no.4
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• pp.204-210
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• 2013

In order to improve osseointegration for biomedical implants, it is crucial to understand the interactions between nanostructured surfaces and cells. In this study, $TiO_2$ nanowires were prepared via Vapor-Liquid-Solid (VLS) process with Sn as a metal catalyst in the tube furnace. Nanowires were grown with $N_2$ heat treatment with their size controlled by the agglomeration of Sn layers in various thicknesses. MC3T3-E1 (pre-osteoblast) were cultured on the $TiO_2$ nanowires for a week. Preliminary results of the cell culture showed that the cells adhere well on the $TiO_2$ nanowires.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.252.2-252.2
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• 2013

ZnO nanostructures have a lot of interest for decades due to its varied applications such as light-emitting devices, power generators, solar cells, and sensing devices etc. To get the high performance of these devices, the factors of nanostructure geometry, spacing, and alignment are important. So, Patterning of vertically- aligned ZnO nanowires are currently attractive. However, many of ZnO nanowire or nanorod fabrication methods are needs high temperature, such vapor phase transport process, metal-organic chemical vapor deposition (MOCVD), metal-organic vapor phase epitaxy, thermal evaporation, pulse laser deposition and thermal chemical vapor deposition. While hydrothermal process has great advantages-low temperature (less than $100^{\circ}C$), simple steps, short time consuming, without catalyst, and relatively ease to control than as mentioned various methods. In this work, we investigate the dependence of ZnO nanowire alignment and morphology on si substrate using of nanosphere template with various precursor concentration and components via hydrothermal process. The brief experimental scheme is as follow. First synthesized ZnO seed solution was spun coated on to cleaned Si substrate, and then annealed $350^{\circ}C$ for 1h in the furnace. Second, 200nm sized close-packed nanospheres were formed on the seed layer-coated substrate by using of gas-liquid-solid interfacial self-assembly method and drying in vaccum desicator for about a day to enhance the adhesion between seed layer and nanospheres. After that, zinc oxide nanowires were synthesized using a low temperature hydrothermal method based on alkali solution. The specimens were immersed upside down in the autoclave bath to prevent some precipitates which formed and covered on the surface. The hydrothermal conditions such as growth temperature, growth time, solution concentration, and additives are variously performed to optimize the morphologies of nanowire. To characterize the crystal structure of seed layer and nanowires, morphology, and optical properties, X-ray diffraction (XRD), field emission scanning electron microscopy (FE-SEM), Raman spectroscopy, and photoluminescence (PL) studies were investigated.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.186-186
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• 2013

종래의 흑연 위주 연료전지 분리판 개발되어 최근 고분자 전해질 막 연료전지가 높은 전력, 낮은 배기 가스 배출, 낮은 작동 온도로 자동차 산업에서 상당한 주목을 받고 있다. 요구사항은 높은 전기 전도도, 높은 내식성, 낮은 가스 투과성, 낮은 무게, 쉬운 가공, 낮은 제조비용이다. Thin film Cr 장비로 저항가열 furnace, sputter 등이 사용된다. 연료전지 분리판의 고전도도, 내부식성 보호막의 고속 증착을 위한 새로운 증착원으로 스퍼터 - 승화형 소스의 가능성을 유도 결합 플라즈마에 금속 봉을 직류 바이어스 함으로써 시도하였다. 유도 결합 플라즈마를 이용하여 승화증착 시스템을 사용하여 OES (SQ-2000)와 QMS (CPM-300)를 사용하여 $N_2$ flow에 따른 유도 결합 플라즈마를 이용한 스퍼터-승화증착 시스템을 사용 하여도 균일한 공정을 하는 것을 확인 하였다. 5 mTorr의 Ar 유도 결합 플라즈마를 2.4 MHz, 500 W로 유지하면서 직류 바이어스 전력을 30 W (900 V, 0.02 A) 인가하고, $N_2$의 유량을 0.5, 1.0, 1.5 SCCM로 변화를 주어 특성을 분석하였다. MID (Multiple Ion Detection) mode에서 유도결합 플라즈마를 이용한 스퍼터-승화 증착 장비를 사용하여 CrN thin flim 성장시켰고, deposition rate은 44.8 nm/min으로 얻을 수 있었다. 또한 $N_2$의 유량이 증가할 수록 bias voltage가 증가하는 것을 확인 할 수 있었다. OES time acquisition을 이용한 공정 분석에서는 $N_2$ 유량을 off 하였을 때 Ar, Cr의 중성 intensity peak이 상승하였고, 시간 경과에 따라 sublimation에 의한 영향이 없는 것을 확인 할 수가 있었다. XRD data에서는 질소 유량이 증가함에 따라 $Cr_2N$이 감소하고, CrN이 증가하는 것을 확인할 수가 있었다. 결정배향성과 Morphology는 다결정 재료의 경도에 영향을 주는 인자이다. CrN 결정 구조의 경우는 (200)면이 경도가 제일 높은데 (200)면에서 성장한 것을 확인 할 수 있었다. 잔류가스 분석 결과로는 일정한 Ar의 유량을 흘렸을 때 $N_2$의 변화량이 비례적인 경향이 보이는 것을 확인 할수 있었다. 또한 $N_2$가 흐르면서도 유도 결합 플라즈마를 이용한 스퍼터-승화 증착 시스템을 사용하면 일정한 공정을 하는 것을 확인 할 수 있었다. 질소의 분압이 유량에 따라서 $3.0{\times}10^{-10}$ Torr에서 $1.65{\times}10^{-9} $Torr까지 일정한 비율로 증가한다. 즉, 이 시스템으로 양산장비 설계를 하여도 가능 하다는 것을 말해준다.

• Korean Journal of Materials Research
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• v.15 no.1
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• pp.31-36
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• 2005

It is well known that PCB (Printed Circuit Board) is a complex mixture of various metals mixed with various types of plastics and ceramics. In this study, high temperature pyre-metallurgical process was investigated to extract valuable metallic components from the PCB scrap. For this purpose, PCB scrap was shredded and oxidized to remove plastic materials, and then, quantitative analyses were made. After the oxidation of the PCB scrap, $30.6wt\%SiO_2,\;19.3wt\%Al_2O_3\;and\;14wt{\%}CaO$ were analyzed as major oxides, and thereafter, a typical composition of $32wt\%SiO_2-20wt\%Al_2O_3-38wt{\%}CaO-10wt\%MgO$ was chosen as a basic slag system for the separation of metallic components. Moreover a size effect of crushed PCB scrap was also investigated. During experiments a high frequency induction furnace was used to melt and separate metallic components. As a result, it was found that the size of oxidized PCB scrap was needed to be less 0.9 m to make a homogeneous liquid slag and to recycle metallic components over $95\%$.