• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.2
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• pp.13-18
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• 2013

In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.10
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• pp.57-64
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• 2002

The structure of conventional CAM(Content Addressable Memory) cell, used to Look-up table scheme in Huffman CODEC, is not performed by being separated in reading, writing and match operation. So, there is disadvantages that the control is complicated, and the floating states of match line force wrong operation to be happened in reading, writing operation. In this paper, in order to improve the disadvantages and proces the data fast, fast Look-up table is designed using DBLCAM(Dual Bit Line CAM)-performing the reading, writing operation and match operation independently and Two-port SRAM being more fast than RAM in an access speed. Look-up table scheme in Huffman CODEC, using DBLCAM and Two-port SRAM proposed in this paper, is designed in Cadence tool, and layout is performed in 0.6${\mu}{\textrm}{m}$ 2-poly 3-metal CMOS full custom. And simulation is peformed with Hspice.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.68-73
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• 2009

This paper presents an easily modifiable structure of a serial peripheral interface (SPI) that is suitable for efficient testing of CMOS RF integrated circuits. The proposed SPI Is designed so that the address size and the accompanying software can be easily adjusted and modified according to the requirements and complexity of RF IC's under development. The hardware architecture and software algorithm to achieve the flexibility are described. The proposed SPI is fabricated in $0.13{\mu}m$ CMOS and successfully verified experimentally with a 2.7GHz fractional-N delta-sigma frequency synthesizer as a device under test.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.360-367
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• 2006

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

• Journal of The Korean Society of Integrative Medicine
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• v.9 no.4
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• pp.85-89
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• 2021

Background : Klippel-Trenaunay-Weber syndrome (KTS) is a rare congenital medical condition characterized by complex vascular malformation. KTS consists of a classic triad of capillary malformation (hemangioma), venous malformations and bone or soft tissue hypertrophy causing limb asymmetry. The aim of this report is to describe management for gait disturbance and foot pain in a Patient with KTS using custom-made total contact insole. Case presentation : A 32-year-old man with KTS presented with a 3-year history of gait disturbance on hard surface due to right first toe pain and Achilles tendon tightness. The patient had soft tissue hypertrophy, varicose veins and port-wine stains over the right lower limb associated with KTS. True leg length discrepancy was 2 cm. We prescribed custom-made total contact insole to protect his deformed foot and correct leg length discrepancy. The insole of right side included wedge shaped heel lift and the insole of left side included full length lift to add extra support on unaffected side. Also, we provided compression stocking and physiotherapy including manual lymphatic drainage for lymphedema and stretching exercise for tightness in right lower extremity. At 3 years follow-up, postural alignment including pelvic obliquity was improved using a custom-made total contact insole. The degree of scoliosis and foot pain were also reduced. Conclusion : An individualized and multidisciplinary approach is essential regarding the complexity of comorbidities in patients with KTS. For patients with KTS, orthotic management should be considered to prevent and correct deformities related to KTS. Active orthotic management, compression stocking and physiotherapy can enhance the quality of life and function in patients.

• Fashion & Textile Research Journal
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• v.24 no.4
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• pp.451-459
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• 2022

This study aimed to develop a a custom-made dress form for draping using a live model's 3D body scan obtained from an entry-level 3D handheld scanners, 3D modeling software and 3D printing technology. A female subject was recruited whose body size fell under the normal (N) body shape criteria suggested by KS K 0051. First, the handheld scanner reduced the length of the legs in scanning, but most of the scanning operations between the neck and crotch levels were conducted accurately. Therefore, this study was designed to develop a torso dress form. The full body 3D scan was edited into a torso shape using ZBrush® software. Using Rhinoceros^® and Materialise's Magics software, a 3D body scan was modeled so that the user could fit two types of mannequin stands (one with a neck fixation from above and one with an insert from below) to the dress form. The body scan was divided into 9 pieces to fit the printable size of the Stratasys 3D printer Fortus 250mc, and the cross-sectional distance from the center to the periphery was downsized by 2 mm. After outputting the dress form scan file with a 3D printer, the dress form was manufactured by the first covering it with a 4 oz nonwoven pad and the second covering with a single jersey material.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.2
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• pp.145-151
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• 2008

This paper proposes the PLL method using positive sequence voltage which is estimated by full-order state observer to find an accurate phase angle under the condition of unbalanced utility voltage. The proposed method uses the full-order state observer instead of existing method(APF All Pass Filter) to find a positive sequence of a utility voltage and this proposed method improves transient response of an estimated phase angle when a three-phase utility voltage becomes unbalanced. To compare proposed method withexisting method, experiments have been done for a phase angle detection of utility voltage when a three-phase utility voltage becomes unbalanced. Their results show that transient state response of proposed method is improved.

• The KIPS Transactions:PartA
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• v.10A no.6
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• pp.671-676
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• 2003

In this paper, we proposed a new First Partial product Addition (FPA) architecture with new compressor (or parallel counter) to CSA tree built in the process of adding partial product for improving speed in the fast parallel multiplier to improve the speed of calculating partial product by about 20% compared with existing parallel counter using full Adder. The new circuit reduces the CLA bit finding final sum by N/2 using the novel FPA architecture. A 5.14nS of multiplication speed of the $16{\times}16$ multiplier is obtained using $0.25\mu\textrm{m}$ CMOS technology. The architecture of the multiplier is easily opted for pipeline design and demonstrates high speed performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.571-574
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• 2008

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.