• Title/Summary/Keyword: flip-through

검색결과 129건 처리시간 0.028초

Dynamics of a Bose-Einstein Condensate on Changing Speeds of an Atomchip Trap Potential

  • Kim, Seung Jin;Noh, Jae June;Kim, Min Seok;Lee, Jin Seung;Yu, Hoon;Kim, Jung Bog
    • Journal of the Optical Society of Korea
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    • 제18권6호
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    • pp.633-638
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    • 2014
  • We report experimental behaviors of condensed $^{87}Rb$ atoms responding to changes in the trap potential of the atomchip. The two-types of adiabatic and non-adiabatic overall changes were implemented by changing the ramp-down speed of the chip-wire current, which can dominantly modify the one-axis magnetic field gradient. Under the adiabatic process, a pure condensate stayed in the initial spin state and collectively oscillated with both monopole and dipole modes, while an atomic cloud above the critical temperature exhibited sound waves in a dense ultracold gas. On the other hand, Bose-Einstein condensate atoms with non-adiabatic perturbation were split into spatially different positions by spin states through spin-flip. We investigated the split ratio among spin states depending on final evaporation frequency. Potential changes, of course, cause collective oscillations regardless of the changing process.

잡음 내성이 큰 단일 출력 레벨 쉬프터를 이용한 500 V 하프브리지 컨버터용 구동 IC 설계 (Design of the Driver IC for 500 V Half-bridge Converter using Single Ended Level Shifter with Large Noise Immunity)

  • 박현일;송기남;이용안;김형우;김기현;서길수;한석봉
    • 한국전기전자재료학회논문지
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    • 제21권8호
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    • pp.719-726
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    • 2008
  • In this paper, we designed driving IC for 500 V resonant half-bridge type power converter, In this single-ended level shifter, chip area and power dissipation was decreased by 50% and 23.5% each compared to the conventional dual-ended level shifter. Also, this newly designed circuit solved the biggest problem of conventional flip-flop type level shifter in which the power MOSFET were turned on simultaneously due to the large dv/dt noise. The proposed high side level shifter included switching noise protection circuit and schmmit trigger to minimize the effect of displacement current flowing through LDMOS of level shifter when power MOSFET is operating. The designing process was proved reasonable by conducting Spectre and PSpice simulation on this circuit using 1${\mu}m$ BCD process parameter.

Maskless Screen Printing Process using Solder Bump Maker (SBM) for Low-cost, Fine-pitch Solder-on-Pad (SoP) Technology

  • Choi, Kwang-Seong;Lee, Haksun;Bae, Hyun-Cheol;Eom, Yong-Sung
    • 마이크로전자및패키징학회지
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    • 제20권4호
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    • pp.65-68
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    • 2013
  • A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process. A selective solder bumping mechanism without the mask is based on the material design of SBM. Maskless screen printing process can implement easily a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology. Its another advantage is ternary or quaternary lead-free SoP can be formed easily. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 ${\mu}m$ is, successfully, formed.

Non-Invasive in vivo Loss Tangent Imaging: Thermal Sensitivity Estimation at the Larmor Frequency

  • Choi, Narae;Kim, Min-Oh;Shin, Jaewook;Lee, Joonsung;Kim, Dong-Hyun
    • Investigative Magnetic Resonance Imaging
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    • 제20권1호
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    • pp.36-43
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    • 2016
  • Visualization of the tissue loss tangent property can provide distinct contrast and offer new information related to tissue electrical properties. A method for non-invasive imaging of the electrical loss tangent of tissue using magnetic resonance imaging (MRI) was demonstrated, and the effect of loss tangent was observed through simulations assuming a hyperthermia procedure. For measurement of tissue loss tangent, radiofrequency field maps ($B_1{^+}$ complex map) were acquired using a double-angle actual flip angle imaging MRI sequence. The conductivity and permittivity were estimated from the complex valued $B_1{^+}$ map using Helmholtz equations. Phantom and ex-vivo experiments were then performed. Electromagnetic simulations of hyperthermia were carried out for observation of temperature elevation with respect to loss tangent. Non-invasive imaging of tissue loss tangent via complex valued $B_1{^+}$ mapping using MRI was successfully conducted. Simulation results indicated that loss tangent is a dominant factor in temperature elevation in the high frequency range during hyperthermia. Knowledge of the tissue loss tangent value can be a useful marker for thermotherapy applications.

FPGA 구조 및 로직 블록의 설계에 관한 연구 (A study on the architecture and logic block design of FPGA)

  • 윤여환;문중석;문병모;안성근;정덕균
    • 전자공학회논문지A
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    • 제33A권11호
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    • pp.140-151
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    • 1996
  • In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

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광모듈 솔더 접합부의 시효 특성에 관한 연구 (Aging Characteristics of Solder bump Joint for High Reliability Optical module)

  • 김남규;김경섭;김남훈;장의구
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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    • pp.204-207
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    • 2003
  • The flip chip bonding utilizing self-aligning characteristic of solder becomes mandatory to meet to tolerances for the optical device. In this paper, a parametric study of aging condition and pad size of sample was conducted. A TiW/Cu UBM structure was adopted and sample was aging treated to analyze the effect of intermetallic compound with time variation. After aging treatment, the tendency to decrease in shear strength was measured and the structure of the fine joint area was observed by using SEM, TEM and EDS. In result, the shear strength was decreased of about 20% in the $100{\mu}m$ sample at $170^{\circ}C$ aging compared with the maximum shear strength of same pad size sample. In the case of the $120^{\circ}C$ aging treatment, 17% of decrease in shear strength was measured at the $100{\mu}m$ pad size sample. Also, intremetallic compound of $Cu_6Sn_5$ and $Cu_3Sn$ were observed through the TEM measurement by using an FIB technique that is very useful to prepare TEM thin foil specimens from the solder joint interface.

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300 nm Diameter Cylinder-Shape 나노패턴 기판을 이용한 LEDs의 광학적 특성 (Optical Characterization of Light-Emitting Diodes Grown on the Cylinder Shape 300 nm Diameter Patterned Sapphire Substrate)

  • 김상묵;김윤석
    • 한국재료학회지
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    • 제29권1호
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    • pp.59-64
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    • 2019
  • This study investigates the optical characteristics of InGaN multiple quantum wells(MQWs) light emitting diodes(LEDs) on planar sapphire substrates(PSSs), nano-sized PSS(NPSS) and micro-sized PSS(MPSS). We obtain the results as the patterning size of the sapphire substrates approach the nanometer scale: The light from the back side of the device increases and the total light extraction becomes larger than the MPSS- and planar-LEDs. The experiment is conducted by Monte Carlo ray-tracing, which is regarded as one of the most suitable ways to simulate light propagation in LEDs. The results show fine consistency between simulation and measurement of the samples with different sized patterned substrates. Notably, light from the back side becomes larger in the NPSS LEDs. We strongly propose that the increase in the light intensity of NPSS LEDs is due to an abnormal optical distribution, which indicates an increase of extraction probability through NPSS.

거리 측정 시스템의 정밀도 향상을 위한 카운터 회로의 설계 (Design of Counter Circuit for Improving Precision in Distance Measuring System)

  • 최진호
    • 한국정보통신학회논문지
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    • 제24권7호
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    • pp.885-890
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    • 2020
  • 거리측정 시스템에서 사용되는 시간-디지털 변환회로는 시작신호와 멈춤신호 사이의 시간 간격을 이용하여 거리를 측정한다. 응답속도를 고려한 시간 간격은 일반적으로 카운터 회로를 이용하여 디지털 정보로 변환한다. 그러므로 정밀도 향상을 위해서는 높은 주파수의 클록 신호가 요구되며, 미세 거리의 측정을 위해서도 높은 주파수의 클록 신호가 필요하다. 본 논문에서는 동일한 주파수를 사용하면서도 거리 측정의 정밀도를 높이기 위한 카운터 회로를 설계하였다. 회로의 설계는 0.18㎛ CMOS 공정을 이용하였으며, 설계된 회로의 동작은 HSPICE 시뮬레이션을 통하여 확인하였다. 시뮬레이션 결과 일반적인 카운터 회로를 사용한 경우에 비해 4배의 향상된 정밀도를 얻을 수 있었다.

계면 트랩에 기반한 BCAT 구조 DRAM의 로우 해머 분석 (Analysis of Row Hammer Based on Interfacial Trap of BCAT Structure in DRAM)

  • 임창영;김연석;권민우
    • 전기전자학회논문지
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    • 제27권3호
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    • pp.220-224
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    • 2023
  • 로우 해머는 특정 행(row)에 연속적으로 액세스할 때 인접한 행에서 비트 플립이 발생하는 현상으로 데이터 손상과 보안 문제, 컴퓨팅 성능 저하를 야기한다. 본 논문은 2ynm DRAM에서 TCAD 시뮬레이션을 통해 로우 해머의 원인과 대응 방법을 분석한다. 실험에서는 트랩의 파라미터와 소자의 구조를 변화시키면서 로우 해머 현상을 재현하고, 트랩 밀도, 온도. 액티브 위스 등과의 관계를 분석한다. 실험 결과, 트랩 파라미터와 소자 구조의 변화는 ΔVcap/pulse에 직접적인 영향을 미치는 것을 확인하였다. 이를 통해 로우 해머에 대한 근본적인 이해와 대응 방안 모색이 가능하고 DRAM의 안정성과 보안을 향상시키는데 기여할 수 있다.

열역학 교과목에 대한 플립러닝 교수법 적용 사례 (A Case Study on the Application of Flipped Learning Methodology to Thermodynamics in Mechanical Engineering)

  • 유경현
    • 공학교육연구
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    • 제25권6호
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    • pp.69-80
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    • 2022
  • In this study, the application of flipped learning methodology to thermodynamics in mechanical engineering was examined, and how university students view flipped learning and the effects of flipped learning were analyzed. To analyze the effects of flipped learning, pre-class survey, assessment on learning in pre-class, team activities during class, and post-class survey were conducted. The analysis was also conducted on 33 students who took the thermodynamics course in mechanical engineering, and the PARTNER flipped learning model was applied to the class. The results of this study are as follows; In the preliminary survey, the students expected that the flip-learning class with team activities and teaching between team members would be helpful in improving their learning. In addition, students recognized that cooperative learning through a team was helpful for learning. The case reflecting the result of pre-learning evaluation to the subject grades showed higher pre-learning evaluation results than the case not reflecting the result of the pre-learning evaluation to the subject grades, and it was found that the pre-learning evaluation was acting as a factor to promote learning in pre-class. In post-class survey, the satisfaction with the flipped learning class was high, indicating that the effectiveness of the flipped learning class applied to the thermodynamics class was excellent.