• 센서학회지
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• 제33권3호
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• pp.134-138
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• 2024

In this study, we propose a ternary D flip-flop using tristate ternary inverters for an energy-efficient ternary circuit design of sequential logic. The tristate ternary inverter is designed by adding the functionality of the transmission gate to a standard ternary inverter without an additional transistor. The proposed flip-flop uses 18.18% fewer transistors than conventional flip-flops do. To verify the advancement of the proposed circuit, we conducted an HSPICE simulation with CMOS 28 nm technology and 0.9 V supply voltage. The simulation results demonstrate that the proposed flip-flop is better than the conventional flip-flop in terms of energy efficiency. The power consumption and worst delay are improved by 11.34% and 28.22%, respectively. The power-delay product improved by 36.35%. The above simulation results show that the proposed design can expand the Pareto frontier of a ternary flip-flop in terms of energy consumption. We expect that the proposed ternary flip-flop will contribute to the development of energy-efficient sensor systems, such as ternary successive approximation register analog-to-digital converters.

• Progress in Superconductivity
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• 제4권2호
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• pp.127-131
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• 2003

We have designed and measured an SFQ(Single Flux Quantum) OR gate for a superconducting ALU (Arithmetic Logic Unit). To optimize the circuit, we used WRspice, XIC and Lmeter for simulations and layouts. The OR gate was consisted of a Confluence Buffer and a D Flip-Flop. When a pulse enters into the OR gate, the pulse does not propagate to the other input port because of the Confluence Buffer. A role of D Flip-Flip is expelling the data when the clock is entered into D Flip-Flop. For the measurement of the OR gate operation, we attached three DC/SFQs, three SFQ/DCs and one RS Flip -Flop to the OR gate. DC/SFQ circuits were used to generate the data pulses and clock pulses. Input frequency of 10kHz and 1MHzwere used to generate the SFQ pulses from DC/SFQ circuits. Output data from OR gate moved to RS flip -Flop to display the output on the oscilloscope. We obtained bias margins of the D Flip -Flop and the Confluence Buffer from the measurements. The measured bias margins $\pm$38.6% and $\pm$23.2% for D Flip-Flop and Confluence Buffer, respectively The circuit was measured at the liquid helium temperature.

• 전기의세계
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• 제13권3호
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• pp.21-27
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• 1964

A method of triggering a series connected complementary transister flip-flop is described. Also measurements have been made for the operation region with respect to the input pulse variation. This circuit is compared with a Eccles-Jordan flip-flop when it used as a Nixie tube driver of a neon lamp driyer.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
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• pp.925-928
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• 1993

In this paper the caracteristics of the fuzzy flip-flop which was proposed as a fuzzy sequential circuit is firstly mentioned. Secondly the circuit construction of typical fuzzy flip-flip circuits using VHDL (Very high speed integrated circuit Hardware Description Language) compiler and simulator is presented. Finally the possibility of the application of the fuzzy sequential circuit will be mentioned.

• Progress in Superconductivity
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• 제3권1호
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• pp.87-90
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• 2001

We designed a high temperature superconducting rapid single flux quantum(RSFQ) T flip-flop(TFF) circuit using Xic and WRspice. According to the optimized circuit parameters, we fabricated the TFF circuit with $Y_1$$Ba_2$Cu$_3$$O_{7-x}$(YBCO) interface-controlled Josephson junctions. The whole circuit was comprised of five epitaxial layers including YBCO ground plane. The interface-controlled Josephson junction was fabricated with natural junction barrier that was formed by interface-treatment process. In addition, we report second design for a new flip-flop without ground palne.e.

• 반도체공학회 논문지
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• 제1권1호
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• pp.14-22
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• 2023

본 논문에서는 dual change-sensing 기법을 사용하여 내부 노드 변환을 최소화시킨 저전력 플립플롭 회로를 제안한다. 제안하는 Dual Change-Sensing Flip-Flop(DCSFF)은 데이터 변환이 존재하지 않는 경우, 기존에 존재하던 플립플롭들 중 동적 전력 소모가 가장 낮다. 65nm CMOS 공정을 사용한 측정 결과에 따르면, conventional Transmission Gate Flip-Flop(TGFF)와 비교하여 data activity 가 0% 와 100% 일때, 각각 98%와 32%의 감소된 전력 소모를 보였다. 또한 Change-Sensing Flip-lop(CSFF)과 비교하여 제안하는 DCSFF 는 30% 의 낮은 전력 소모를 보였다.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 2000년도 High Temperature Superconductivity Vol.X
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• pp.189-192
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• 2000

We fabricated rapid single-flux-quantum RS flip-flop circuits with and without Y$_1$Ba$_2$Cu$_3$O$_{7-{\delta}}$(YBCO) ground plane. The circuit consists of SNS-type ramp-edge Josephson junctions that have cobalt-doped YBCO and Sr$_2$AITaO$_6$(SAT) for barrier layer and insulator layer, respectively. The fabricated Josephson junction showed a typical RSJ-like current-voltage(I-V) characteristics above 50K. We sucessfuly demonstrated RS flip-flop at temperatures around 50K. The RS flip-flop fabricated on ground plane showed more definite set and reset state in voltage-flux(V-${\phi}$) modulation curve for read SQUID, which may be attributed to a shielding effect of the YBCO ground plane.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.347-350
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• 2000

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are fabricated with ternary voltage mode NOR, NAND, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, a lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.25 micron CMOS technology and 2.5 volts supply voltage. The Architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• 한국소프트웨어감정평가학회 논문지
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• 제15권1호
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• pp.103-107
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• 2019

최근 저전력 고속 디지털 데이터 통신을 구현 하기위해 많은 기술들이 개발되고 있는 추세이며 듀티사이클 보정에 관련된 기술도 그중 하나이다. 본 논문에서는 전압제어 링 발전기용 저-면적 듀티사이클 보정 회로를 제안하였다. 듀티사이클 보정 회로는 전압제어 링 발진기의 180도 위상차이를 이용하여 듀티사이클을 보정하는 회로이며, 제안된 저-면적 듀티사이클 회로는 기존의 플립플롭을 TSPC(True Single Phase Clocking) 플립플롭으로 변경하여 회로를 구성하였고 이로 인하여 저-면적 고성능 회로를 구현하였다. 일반적인 플립플롭을 대신하여 TSPC플립플롭을 사용하여 기존 회로 대비 저-면적으로 회로 구현이 가능하며 고속 동작에 용이하여 저-전력용 고성능 회로에 활용될 것으로 기대된다.

• Progress in Superconductivity
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• 제5권1호
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• pp.13-16
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• 2003

In this work, we have studied about an RSFQ (Rapid Single Flux Quantum) switch element. The circuit was designed, simulated, and laid out for mask fabrication. The switch cell was composed of a D flip-flop, a splitter, a confluence buffer, and a switch core. The switch core determined if the input data could pass to the output. “On” and o“off” controls in the switch core could be possible by utilizing an RS flip-flop. When a control pulse was input to the “on” port, the RS flip-flop was in the set state and passed the input pulses to the output port. When a pulse was input to the “off” port, the RS flip-flop was in the reset state and prevented the input pulses from transferring to the output port. We simulated and optimized the switch element circuit by using Xic, WRspice, and Julia. The minimum circuit margins in simulations were more than $\pm$20%. We also performed the mask layout of the circuit by using Xic and Lmeter.