• Korean Journal of Materials Research
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• 제14권8호
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• pp.542-546
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• 2004

We report a new fabrication process for high performance triode type CNT field emitters and their superior electrical properties. The CNT-based triode-type field emitter structure was fabricated by the conventional semiconductor processes. The keys of the fabrication process are spin-on-glass coating and trim-and-leveling of the carbon nanotubes grown in trench structures by employing a chemical mechanical polishing process. They lead to strong adhesion and a uniform distance from the carbon nanotube tips to the electrode. The measured emission property of the arrays showed a remarkably uniform and high current density. The gate leakage current could be remarkably reduced by coating of thin $SiO_{2}$ insulating layer over the gate metal. The field enhancement factor(${\beta}$) and emission area(${\alpha}$) were calculated from the F-N plot. This process can be applicable to fabrication of high power CNT vacuum transistors with good electrical performance.

• Journal of Korean Vacuum Science & Technology
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• 제3권1호
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• pp.38-42
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• 1999

Using the LOCOS process, we have fabricated the lateral type polysilicon field emission triodes with poly-Si/oxide/Si structure and investigated their current-voltage characteristics for three biasing modes of operation. The fabricated devices exhibit excellent electrical performances such as a relatively low turn-on anode voltage of 14 V at VGC = 0V, a stable and high emission current of 92${\mu}$A/triode over 90 hours, a small gate leakage current of 0.23 ${\mu}$A/triode and an outstanding transconductance of 57${\mu}$S/5triodes at VGC = 5V and VAC = 26V. these superior electrical operation is believed to be due to a large field enhancement effect, which is related to the sharp cathode tips produced by the LOCOS process as well as the high aspect ratio (height /radius ) of the cathode tip end.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1253-1256
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• 2007

A display device combining plasma display panel (PDP) and field emission display (FED) is proposed to achieve high luminous efficiency. The device can avoid the main energy loss channels of both PDP (ion loss) and FED (low CL efficiency). $2{\sim}6$”-diagonal test panels with carbon nano-tube (CNT) electron emitter and Xenon ambient gas showed the luminous efficiency of 4.14lm/W and brightness of $263cd/m^2$ at 35V (1kHz, 1% duty), indicating that it is a good candidate for the low voltage driven, highly efficient next generation display.

• The Transactions of the Korean Institute of Electrical Engineers C
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• 제48권9호
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• pp.656-661
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• 1999

As a fundamental study for FED tubeless packaging, sodalime-sodalime electrostatic bonding was performed by using on the developed bonding mechanism. Thebonding properties of the bonded sodalime-sodalime structure were investigated through SEM and SIMS analyses. Mo-tip FEA was vacuum-packaged by the developed bonding process and the packaged device generated the field emission current.

• The Transactions of the Korean Institute of Electrical Engineers C
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• 제48권9호
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• pp.662-664
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• 1999

We fabricated AC-TFEL device having cone-shaped Si micro-tip reflector array based on the process which have been conventionally employed for the Si-tip field emitter array in FED system. As a result, the AC-TFEL device having a new geometrical structure could generate well concentrated visible white-light from 3600 reflectors/pixel under bipolar pulse excitation mode only by edge-emission mechanism.

• Proceedings of the KIEE Conference
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3274-3275
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• 1999

This paper presents a new method of spacer assembly using anodic bonding method which is very simple and clean. The spacer having $100{\mu}m(W){\times}2.1{\mu}m(H)$ was bonded on amorphous silicon film of anode plate. Then, the vertical-type electrode was used for assembling of spacer in high voltage field emission display. In these results, we suggested that the vertical-type electrode provided spacer alignment for high aspect ratio and more simple batch process than conventional method.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2006년도 6th International Meeting on Information Display
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• pp.1219-1224
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• 2006

This study investigates the effect of $NH_3$ gas upon the growth of carbon nanotubes (CNTs) using thermal chemical vapor deposition. It is considered that the CNT synthesis occurs mainly through two steps, clustering of catalyst particles and subsequent growth of CNTs. We thus introduced $NH_3$ during either an annealing or growth step. When $NH_3$ was fed only during annealing, CNTs grew longer and more highly crystalline with diameters unchanged. An addition of $NH_3$ during growth, however, resulted in shorter CNTs with lower crystallinity while increased their diameters. Vertically aligned, highly populated CNT samples showed poor field emission characteristics, leading us to apply post-treatments onto the CNT surface. The CNTs were treated by adhesive tapes or etched back by dc plasma of $N_2$ to reduce the population density and the radius of curvatures of CNTs. We discuss the morphological changes of CNTs and their field emission properties upon surface treatments.

• Journal of Information Display
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• 제2권3호
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• pp.60-65
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• 2001

Lateral type poly-silicon field emitters were fabricated by utilizing the LOCOS (Local Oxidation of Silicon) process. For the implementation 'of an ideal field emission device with quasi-zero tunneling barrier, a new and fundamental approach has used conducted by introducing an intelligent carbon-based thin layer on the cathode tip surface via a field-assisted self-aligning of carbon (FASAC) process. Fundamental lowering of the turn-on field for the electron emission was feasible through the control of both the tip shape and surface barrier height.

• Transactions on Electrical and Electronic Materials
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• 제3권1호
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• pp.4-8
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• 2002

The typical mold method for FED (field emission display) fabrication is used to form a gate electrode, a gate oxide layer, and emitter tip after fabrication of a mold shape using wet-etching of Si substrate. However, in this study, new mold method using a side wall space structure was developed to make sharp emitter tips with the gate electrode. In new method, gate oxide layer and gate electrode layer were deposited on a Si wafer by LPCVD (low pressure chemical vapor deposition), and then BPSG (Boro phosphor silicate glass) thin film was deposited. After then, the BPSG thin film was flowed into the mold at high temperature in order to form a sharp mold structure. TiN was deposited as an emitter tip on it. The unfinished device was bonded to a glass substrate by anodic bonding techniques. The Si wafer was etched from backside by KOH-deionized water solution. Finally, the sharp field emitter array with gate electrode on the glass substrate was formed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권6호
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• pp.23-30
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• 2005

In this paper, OPPS(oxidized porous poly-silicon) field emitters were fabricated by using various emitter-electrode metal and these electron emission characteristics were investigated for different thermal annealing effects. The addressed OPPS field emitter with Pt/Ti emitter electrode annealed at $300^{\circ}C$-1hr showed the efficiency of $2.98\%$ at $V_{ps}$=12 V and one annealed at $350^{\circ}C$-1hr showed the highest efficiency of $3.37\%$at $V_{ps}$=16V. They are resulted from the improvement of interfacial contact characteristics of thin emitter metal to an oxidized porous poly-silicon and the decrease of electrical resistance of emitter metal. The brightness of the OPPS field emitter increases linearly in $V_{ps}$ and after oxidation process for $900^{\circ}C$-50min, the brightness of the OPPS field emitter with the as-deposited Pt/Ti emitter electrode was 3600 cd/$m^2$ at the $V_{ps}$=15 V, 6260 cd/$m^2$ at the $V_{ps}$=20 V. Thermal treatment improved the adhesion between the Ti buffer layer and the oxidized porous poly-silicon and also played an important role in the uniform distribution of electric field to the emitter electrode.