• Journal of IKEEE
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• v.27 no.1
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• pp.65-70
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• 2023

More than 10,000 Carbon NanoTube Field Effect Transistors (CNTFETs), which have advantages such as high carrier mobility, large saturation velocity, low intrinsic capacitance, flexibility, and transparency, have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes. Three-dimensional multilayer structure of the CNTFET semiconductor chip and various CNTFET manufacturing process research increase the possibility of making the hybrid MOSFET-CNTFET semiconductor chip which combines conventional MOSFETs and CNTFETs together in a semiconductor chip. This paper discusses a methodology to design 6T binary SRAM using hybrid MOSFET-CNTFET. By utilizing the existing MOSFET SRAM or CNTFET SRAM design method, we will introduce a method of designing a hybrid MOSFET-CNTFET SRAM and compare its performance with the conventional MOSFET SRAM and CNTFET SRAM.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.25-26
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• 2011

In this paper, we investigated the effect of various annealing processes on the electrical characteristics of oxide thin film transistors (TFTs). When we annealed the TFT devices before and after source/drain (S/D) process, we could observe the different electrical characteristics of oxide TFTs. When we annealed the TFTs after deposition of transparent indium zinc oxide S/D electrodes, the annealing process decreased the contact resistance but increased the resistivity of S/D electrodes. The field effect mobility, subthreshold slope and threshold voltage of the oxide TFTs annealed before and after S/D process were 5.83 and 4.47 $cm^2$/Vs, 1.20 and 0.82 V/dec, and 3.92 and 8.33 V respectively. To analyze the differences, we measured the contact resistances and the carrier concentrations using transfer length method (TLM) and Hall measurement.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.2
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• pp.169-174
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• 2014

As a versatile processing method for nanoscale memory integration, laser-induced epitaxial growth is proposed for the fabrication of vertical Si channel (VSC) transistor. The fabricated VSC transistor with 80 nm gate length and 130 nm pillar diameter exhibited field effect mobility of $300cm^2/Vs$, which guarantees "device quality". In addition, we have shown that this VSC transistor provides memory operations with a memory window of 700 mV, and moreover, the memory window further increases by employing charge trap dielectrics in our VSC transistor. Our proposed processing method and device structure would provide a promising route for the further scaling of state-of-the-art memory technology.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.245-245
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• 2008

In this work, we describe the characterization of PVP films synthesized by spin-coater method and fabricate OTFTs of a bottom gate structure using pentacene as the active layer and polyvinylphenol (PVP) as the gate dielectric on Au gate electrode. We investigated the surface and electrical properties of PVP layer using an AFM method and MIM structure, and estimated the device properties of OTFTs including $I_D-V_D$, $I_D-V_G$, threshold voltage $V_T$, on/off ratio, and field effect mobility.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.745-748
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• 2007

Hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) were fabricated on a flexible metal substrate at $150\;^{\circ}C$. To increase the stability of the flexible a-Si:H TFTs, they were thermally annealed at $230\;^{\circ}C$. The field effect mobility was reduced because of the strain in a- Si:H TFT under thermal annealing.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.12
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• pp.53-58
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• 1998

A buried channel poly-Si TFT (BCTFT) for application of high performance integrated circuits has been proposed and fabricated. BCTFT has unique features, such as the moderately-doped buried channel and counter-doped body region for conductivity modulation, and the fourth terminal entitled back bias for preventing kink effect. The n-type and p-type BCTFT exhibits superior performance to conventional poly-Si TFT in ON-current and field effect mobility due to moderate doping at the buried channel. The OFF-state leakage current is not increased because the carrier drift is suppressed by the p-n junction depletion between the moderately-doped buried channel and the counter-doped body region.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.12
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• pp.559-561
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• 2003

We report a new excimer laser annealing method which successfully results in a single grain boundary formation in the channel of polycrystalline silicon thin film transistor. The proposed method is based on lateral grain growth and employs aluminum patterns which act as selective beam mask and lateral heat sink. The maximum grain size obtained by the proposed method is about 1.6${\mu}{\textrm}{m}$ in the length. The grainboundaries should be arranged parallel with the direction of current flow for the best device performance, so we propose a new device fabrication method and a new poly-Si TFT structure. Poly-Si TFT fabricated by the proposed method exhibits considerably improved electrical characteristics, such as high field effect mobility exceeding 240 $cm^2$/Vsec.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.430-430
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• 2010

MICC 방법으로 제작된 TFT는 large grain과 그에 따른 grain boundary의 감소로 인하여여, 소자의 전기적 특성을 좋게 할 수 있다. 본 연구에서는 bi-layer channel의 large grain size TFT를 제작하여 소자의 전기적 특성을 비교하였다. Channel의 width / length의 크기는 각 각의 경우 $7/5{\times}2$, $10/5{\times}2$, $15/5{\times}2$ (${\mu}m$)로 하였다. 소자의 성능 측정 결과 Field-effect mobility의 경우에는 channel width가 증가할 수록 감소하는 경향성을 나타내었으며, Threshold voltage의 경우에는 조금 감소하는 경향성은 있었으나 변화의 폭이 매우 작았다. Output characteristics 의 경우에는 모든 set에서 좋은 saturation 특성을 보였다. 이것은 current croding이 없었다는 것을 의미하는데, 큰 grain size로 인한 효과로 해석 할 수 있다. 본 연구에서는 bi-layer channel에서 corner effect에 중점을 두어 소자의 전기적 특성 변화에 대하여 논하였다.

• Journal of Adhesion and Interface
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• v.21 no.3
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• pp.107-112
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• 2020

Recently, the atomically thin transition-metal dichalcogenide (TMD) semiconductors have attracted much attention owing to their remarkable properties such as tunable bandgap with high carrier mobility, flexibility, transparency, etc. However, because these TMD materials have a significant drawback that they are easily degraded in an ambient environment, various attempts have been made to improve chemical stability. In this research article, I report a method to improve the air stability of WSe₂ one of the TMD materials via surface passivation with an h-BN insulator, and its application to field-effect transistors (FETs). With a modified hot pick-up transfer technique, a vertical heterostructure of h-BN/WSe₂ was successfully made, and then the structure was used to fabricate the top-gate bottom-contact FETs. The fabricated WSe₂-based FET exhibited not only excellent air stability, but also high hole mobility of 150 ㎠/Vs at room temperature, on/off current ratios up to 3×10⁶, and 192 mV/decade of subthreshold swing.

• New Physics: Sae Mulli
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• v.68 no.11
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• pp.1192-1195
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• 2018

We studied the electrical properties of organic thin-film transistors (OTFTs) fabricated at different deposition rates by measuring the field-effect mobility and the threshold voltages. As the active layer, pentacene thin film with a thickness of 50 nm was deposited at a rate of $0.05{\AA}/s$ to $1.14{\AA}/s$. The thickness of the drain-source gold electrode was 50 nm. The mobility was $1.9{\times}10^{-1}cm^2/V{\cdot}s$ at a deposition rate of $0.05{\AA}/s$, the mobility increased to $5.2{\times}10^{-1}cm^2/V{\cdot}s$ when the deposition rate was increased to $0.4{\AA}/s$, and then the mobility decreased to $6.5{\times}10^{-1}cm^2/V{\cdot}s$ when the deposition rate decreased to $1.14{\AA}/s$. Thus, the mobility of pentacene OTFTs was observed to depend on the thermal deposition rate.