• The Transactions of The Korean Institute of Electrical Engineers
• /
• v.64 no.12
• /
• pp.1737-1741
• /
• 2015

A multi-channel CMOS transimpedance amplifier(TIA) array is realized in a $0.18-{\mu}m$ CMOS technology for the applications of panoramic scan LADAR systems. Each channel consists of a PIN photodiode and a feed-forward TIA that exploits an inverter input stage followed by a feed-forward common-source amplifier so as to achieve lower noise and higher gain than a conventional voltage-mode inverter TIA. Measured results demonstrate that each channel achieves $76-dB{\Omega}$ transimpedance gain, 720-MHz bandwidth, and -20.5-dBm sensitivity for $10^{-9}$ BER. Also, a single channel dissipates the power dissipation of 30 mW from a single 1.8-V supply, and shows less than -33-dB crosstalk between adjacent channels.

• Journal of the Korean Society for Precision Engineering
• /
• v.30 no.9
• /
• pp.951-959
• /
• 2013

In order to improve the speed performance of the direct drive mechanical systems, a comprehensive analysis of the velocity ripples of blushless DC motors should be required. Every motor has a certain level of torque ripples when it generates power, and the generated torque ripple also makes the velocity ripples in the final output stage in speed control system. In this paper, a novel algorithm for reducing velocity ripples is proposed based on the modeling of torque ripples for BLDC motors. Various algorithms have been made for torque ripples, but usually they should be installed inside the amplifier logic, result in the difficulties of flexibility for various kinds of torque ripples. The proposed algorithm was developed for being ported in the controller not the amplifier, and it has the capability of the automatic compensation adjustment. The performance of the proposed algorithm was verified by effective simulations and experiments.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.38 no.1
• /
• pp.20-26
• /
• 2001

Predistorter linearizer having small size and good efficiency is frequently used in High Power Amplifier linearizer system. In this paper, the amount of IMD signal cancellation according to amplitude and phase of predistorter in predistorter type lincarizer is investigated by new experiment method. In the combining method of predistorter type, IMD signal is combined at the amplifier input port, the magnitude and phase of combining signals cannot be easily expected due to different magnitude and phase of incoming signals. By experiment, it is measured that Predistorter linearizer has lower amount of lMD signal cancellation than thoce of Feedforward linearizer at the same condition (amplitude and phase).

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.37 no.2
• /
• pp.91-97
• /
• 2000

Tn this paper, a novel control circuit applicable to the error sensor loop block in the feedforward linearizer system is proposed. The proposed control circuit is applied to the error sensor loop block, where in the 11dB power range, it operates stably, and makes main carrier signals to be eliminated more than 40dB below 3$\^$rd/ order IM level. In the operating point, the amplitude control error is 0.05∼0.12dB, and the phase control error is smaller than 0.02。. It is verified theoretically as well as experimentally that the control circuit can precisely compensate the variation of nonlinear characteristics in a high power amplifier, due to the variations of input power, operating temperature, humidity and the other system environments.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.15 no.5
• /
• pp.335-342
• /
• 2022

In this paper, a single-bit 3rd-order feedforward delta sigma modulator is proposed for audio applications. The proposed modulator is based on a class-C inverter for low voltage and power applications. For the high-precision requirement, the class-C inverter with regulated cascode structure increases its DC gain and acts as a low-voltage subthreshold amplifier. The proposed Class-C inverter-based modulator is designed and simulated in 180-nm CMOS process. With no performance loss and a low supply voltage compatibility, the proposed class-C inverter-based switched-capacitor modulator achieves high power efficiency. This design achieves an signal-to-noise-and-distortion ratio (SNDR) of 93.9 dB, an signal-to-noise ratio (SNR) of 108 dB, an spurious-free dynamic range (SFDR) of 102 dB, and a dynamic range (DR) of 102 dB at a signal bandwidth of 20 kHz and a sampling frequency of 4 MHz, while only using 280 μW of power consumption from a 0.8-V power supply.

• ETRI Journal
• /
• v.30 no.5
• /
• pp.729-734
• /
• 2008

Wireless communication systems, such as WLAN or Bluetooth receivers, employ preamble data to estimate the channel characteristics, introducing stringent settling-time constraints. This makes the use of traditional closed-loop feedback automatic gain control (AGC) circuits impractical for these applications. In this paper, a compact feedforward AGC circuit is proposed to obtain a fast-settling response. The AGC has been implemented in a 0.35 ${\mu}m$ standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 dB to 21 dB in 3 dB steps through a digital word. The settling time of the circuit is below 0.25 ${\mu}s$.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.47 no.8
• /
• pp.13-22
• /
• 2010

Independent-Gate-Mode Double-Gate(IGM-DG) MOSFET overcomes the limitation of bulk-MOSFET's channel controllability and enables to control the front and back-gate voltages independently. Therefore, circuit designs utilizing the IGM-DG MOSFETs provide the advantage of setting 4-terminal freely, hence achieving not only the performance improvement but also the larger scale integration. This paper presents a 15Gb/s optical receiver with a 1.0V power supply voltage, which consists of a transimpedance amplifier (TIA), a feedforward limiting amplifier (LA), and an output buffer. HSPICE simulations were conducted to confirm the circuit performance, and also to verify the circuit stability issues which may occur from the variations of process and supply voltage.

• Proceedings of the KIEE Conference
• /
• 1995.07c
• /
• pp.1120-1122
• /
• 1995

This paper presents a 2-stage, simple, power-efficient 3V CMOS operational amplifier and its equation based design optimization. Because of its simple structure, it is very suitable as a VLSI library cell in analog/digital mixed-mode systems. The op-amp, which contains a constant-$g_m$ rail-to-rail input stage and a simple feedforward class-AB rail-to-rail output stage, is analyzed and the results are presented in the form of design equations and procedures, which provide an insight into the trade-offs among performance requirements. The results of SPICE simulations are shown to agree very welt with the use of design equations.

• ETRI Journal
• /
• v.45 no.4
• /
• pp.690-703
• /
• 2023

Multistage amplifiers have become appropriate choices for high-speed electronics and data conversion. Because of the large number of high-impedance nodes, frequency compensation has become the biggest challenge in the design of multistage amplifiers. The new compensation technique in this study uses two differential stages to organize feedforward and feedback paths. Five Miller loops and a 500-pF load capacitor are driven by just two tiny compensating capacitors, each with a capacitance of less than 10 pF. The symbolic transfer function is calculated to estimate the circuit dynamics and HSPICE and TSMC 0.18 ㎛. CMOS technology is used to simulate the proposed five-stage amplifier. A straightforward iterative approach is also used to optimize the circuit parameters given a known cost function. According to simulation and mathematical results, the proposed structure has a DC gain of 190 dB, a gain bandwidth product of 15 MHz, a phase margin of 89°, and a power dissipation of 590 ㎼.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.25 no.5
• /
• pp.358-368
• /
• 2020

Grid-connected inverters (GCIs) based on renewable energy sources play an important role in enhancing the sustainability of a society. Harmonic standards, such as IEEE 519 and P1547, which require the total harmonic distortion (THD) of the output current to be less than 5%, should be satisfied when GCIs are connected to a grid. However, achieving a current THD of less than 5% is difficult for GCIs with an output filter under a distorted grid condition. In this study, a novel harmonic compensation method that uses a digital lock-in amplifier (DLA) is proposed to eliminate harmonics effectively at the output of GCIs. Accurate information regarding harmonics can be obtained due to the outstanding performance of DLA, and such information is used to eliminate harmonics with a simple proportional-integral controller in a feedforward manner. The validity of the proposed method is verified through experiments with a 5 kW single-phase GCI connected to a real grid.