• 제목/요약/키워드: fault propagation

검색결과 156건 처리시간 0.028초

HVDC 선로 내 초전도 한류기와 전력기기들의 복합 구성을 통한 고장 검출에 관한 연구 (The Study on The Complex Composition By SFCL and Power Equipments for Fault Detection in HVDC Line)

  • 김명현;김재철
    • 전기학회논문지
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    • 제67권8호
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    • pp.1113-1118
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    • 2018
  • Protection in HVDC(High Voltage Direct Current) have the very fast velocity of fault detection. Because Fault in HVDC has the fast propagation, large currents, high interruption cost. The focus to velocity caused possibility of errors like a detection error like a high impedance fault. In this paper, Proposed complex composition for get the reliability and velocity. That used SFCL(Super Conducting Fault Current Limiter), Protection Zone and DTS(Distributed Temperature Sensing). The SFCL was detect the fault by quench and DTS&Protection Zone were perceive the detect by variation too. To examine the proposed method, PSCAD/EMTDC simulated. The results of simulation, proposed methods could the detect of fault to whole HVDC line. And that improved the reliability of fault clearing.

추계학적 선진원 모델과 층상반무한체에서의 탄성파 전파 해석법에 의한 지진 지반운동 합성 (Synthesis of Earthquake Ground Motion by Combining Stochastic Line Source Model with Elastic Wave Propagation Analysis Method in a Layered Half Space)

  • 김재관;권기준
    • 한국강구조학회 논문집
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    • 제8권3호통권28호
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    • pp.97-105
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    • 1996
  • A Stochastic line source model is developed to simulate the seismic wave field generated during the rupture propagation process along a fault plane of which length is much larger than its width. The fault plane is assumed to consist of randomly distributed slip zones and barriers and each slip zone is modeled as a point source. By combining the newly developed source model with wave propagation analysis method in a layered 3-D visco-elastic half space, synthetic seismograms are obtained. The calculated accelerograms due to vertical dip slip and strike slip line sources are presented.

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Robust process fault diagnosis with uncertain data

  • Lee, Gi-Baek;Mo, Kyung-Joo;Yoon, En-Sup
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1996년도 Proceedings of the Korea Automatic Control Conference, 11th (KACC); Pohang, Korea; 24-26 Oct. 1996
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    • pp.283-286
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    • 1996
  • This study suggests a new methodology for the fault diagnosis based on the signed digraph in developing the fault diagnosis system of a boiler plant. The suggested methodology uses the new model, fault-effect tree. The SDG has the advantage, which is simple and graphical to represent the causal relationship between process variables, and therefore is easy to understand. However, it cannot handle the broken path cases arisen from data uncertainty as it assumes consistent path. The FET is based on the SDG to utilize the advantages of the SDG, and also covers the above problem. The proposed FET model is constructed by clustering of measured variables, decomposing knowledge base and searching the fault propagation path from the possible faults. The search is performed automatically. The fault diagnosis system for a boiler plant, ENDS was constructed using the expert system shell G2 and the advantages of the presented method were confirmed through case studies.

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신경회로망을 이용한 송전계통의 고속계전기용 고장유형분류 및 고장거리 추정방법 (Fault Type Classification and Fault Distance Estimation for High Speed Relaying Using Neural Networks in Power Transmission Systems)

  • 이화석;윤재영;박준호;장병태
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1996년도 하계학술대회 논문집 B
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    • pp.808-810
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    • 1996
  • In this paper, neural network, which has learning capability, is used for fault type classification and fault section estimation for high speed relaying. The potential of the neural network approach is demonstrated by simulation using ATP. The instantaneous values of voltages and currents are used the inputs of neural networks. This approach determines the fault section directly. In this paper, back-propagation network(BPN) is used for fault type classification and fault section estimation and can use for high speed relaying because it determines fault section within a few msec.

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자기결합형 고온초전도한류기의 과도전류 해석 (The Analysis of Transient currents in a Magnetic coupling High-Tc superconducting Fault Current Limiter)

  • 주민석;추용;임도현;고태국
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1995년도 하계학술대회 논문집 A
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    • pp.24-26
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    • 1995
  • In this paper, we investigated transient fault currents in a magnetic coupling High-Tc superconducting current limiter(HCL). It has an important effect on the reliability and stability of the power system. In order to analyze transient fault characteristics of HCL, we fabricated a magnetic coupling HCL and tested it in different fault conditions. An important parameter of design and manufacture which makes HCL inherently reliable is reduction of inrush fault currents. Without inrush fault currents, the currents flowing under such conditions can be limited to a desired-value within one cycle. Inrush fault current depends on saturation, normal spot propagation velocity, turns ratio and the fault angle.

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고속 인터럽터를 적용한 한류기의 전류제한요소에 따른 특성 (Characteristics of a FCL Applying Fast Interrupter According to the Current Limitation Elements)

  • 임인규;최효상;정병익
    • 전기학회논문지
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    • 제61권11호
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    • pp.1752-1757
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    • 2012
  • With the development in industry, power demand has increased rapidly. As consumption of power has increased, Demand for new power line and electric capacity has risen. However, in the event of fault, problems occur in extending the range of fault coverage and increasing fault current. In these reasons, protection devise is recognized as the prevention of an accident and fault current. This paper dealt with minimizing fault propagation and limiting fault current by adjusting fault current limiter (FCL) with fast interrupter. At this point, we compared and analyzed characteristics between non-inductive resistance and fault current which is limited by superconducting units. In normal state of the power system, power was supplied to the load, but when fault occurred, the interrupter was operated as CT which detected the over-current. Its operation made the limitation of fault current through a FCL. We concluded that the limiter using superconducting units was more efficient with the increase of power voltage. Superconducting fault current limiter with the fast interrupter prevented the spread of a fault, and improved reliability of power system.

진행파 모드 분해 기법을 이용한 고속 고장점 표정 (A fast fault location method using modal decomposition technique of traveling wave)

  • 조경래;홍준희;김성수;강용철;박종근
    • 대한전기학회논문지
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    • 제45권2호
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    • pp.167-174
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    • 1996
  • In this paper, a fault location algorithm is presented, which uses novel signal processing techniques and takes a new paradigm to overcome some drawbacks of the conventional methods. This new method for fault location on electric power transmission lines uses only one-terminal fault signals. The main feature of the method is hat it uses the high frequency components in fault signal and considers the influence of the source network by using a traveling wave propagation characteristics. As a result, we can develop a high speed, good accuracy fault locator.

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혼합형 조합 회로용 고장 시뮬레이션 시스템의 설계 및 구현 (Design and Implementation of a Fault Simulation System for Mixed-level Combinational Logic Circuits)

  • 박영호;손진우;박은세
    • 한국정보처리학회논문지
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    • 제4권1호
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    • pp.311-323
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    • 1997
  • 본 논문에서는 게이트 레벌 소자와 스위치 레벨 소자가 함께 사용한 혼합형 조합 회로에서의 고착 고장(stuck-at fault) 검출을 위한 고장 시뮬레이션에 대하여 기술 한다. 실용적인 혼합형 회로의 고장 검출용으로 사용하기 위하여 게이트 레벨 및 정 적 스위치 레벨 회로는 물론 동적 스위치 레벨의 회로들도 처리할 수 있도록 한다. 또한, wired 논리 소자에서의 다중 신호 충돌 현상을 해결하기 위하여 새로운 6치 논 리값과 연산 규칙을 정의하여 신호 세기의 정보와 함께 사용한다. 고장 시뮬레이션의 기본 알고리즘으로는 게이트 레벨 조합 회로에서 주로 사용되는 병렬 패턴 단일 고장 전달(PPSFP:parallel pattern single fault propagation) 기법을 스위치 레벨 소자에 확장 적용한다. 마지막으로 스위치 레벨 소자로 구현된 ISCAS85 벤치 마크 회로와 실 제 혼합형 설계 회로에 대한 실험 결과를 통하여 본 연구에서 개발된 시스템의 효율 성을 입증한다.

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지연 고장 테스팅에 대한 고장 검출율 메트릭 (Fault Coverage Metric for Delay Fault Testing)

  • 김명균;강성호;한창호;민형복
    • 대한전자공학회논문지SD
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    • 제38권4호
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    • pp.266-276
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    • 2001
  • 빠른 반도체 기술의 발전으로 인하여 VLSI 회로의 복잡도는 크게 증가하고 있다. 그래서 복잡한 회로를 테스팅하는 것은 아주 어려운 문제로 대두되고 있다. 또한 집적회로의 증가된 집적도로 인하여 여러 가지 형태의 고장이 발생하게 됨으로써 테스팅은 더욱 중요한 문제로 대두되고 있다. 이제까지 일반적으로 지연 고장 테스팅에 대한 신뢰도는 가정된 고장의 개수에 대한 검출된 고장의 개수로 표현되는 전통적인 고장 검출율로서 평가되었다. 그러나 기존의 교장 검출율은 고장 존재의 유무만을 고려한 것으로써 실제의 지연 고장 테스팅에 대한 신뢰도와는 거리가 있다. 지연 고장 테스팅은 고착 고장과는 달리 경로의 진행 지연과 지연 결함 크기 그리고 시스템 동작 클럭 주기에 의존하기 때문이다. 본 논문은 테스트 중인 경로의 진행 지연과 지연 결함 크기를 고려한 새로운 고장 검출율 메트릭으로서지연 결함 고장 검출율(delay defect fault coverage)을 제안하였으며, 지연 결함 고장 검출율과 결함 수준(defect level)과의 관계를 분석하였다.

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인공 신경 회로망을 이용한 화학공정의 이상진단 시스템 (A fault diagnostic system for a chemical process using artificial neural network)

  • 최병민;윤여홍;윤인섭
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1990년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 26-27 Oct. 1990
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    • pp.131-134
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    • 1990
  • A back-propagation neural network based system for a fault diagnosis of a chemical process is developed. Training data are acquired from FCD(Fault-Consequence Digraph) model. To improve the resolution of a diagnosis, the system is decomposed into 6 subsystems and the training data are composed of 0, 1 and intermediate values. The feasibility of this approach is tested through case studies in a real plant, a naphtha furnace, which has been used to develop a knowledge based expert system, OASYS (Operation Aiding expert SYStem).

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