• Journal of the Optical Society of Korea
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• 제18권1호
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• pp.65-70
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• 2014

This paper presents the simulation and design of an all-optical subtractor using a quantum-dot semiconductor optical amplifier Mach-Zehnder interferometer (QD-SOA MZI) structure consisting of two cascaded switches, the first of which produces the differential bit. Then the second switch produces the borrow bit by using the output of the first switch and the subtrahend data stream. Simulation results were obtained by solving the rate equations of the QD-SOA. The effects of QD-SOA length, peak power and current density have been investigated. The designed gate can operate at speeds of over 250 Gb/s. The simulation results demonstrate a high extinction ratio and a clear and wide-opening eye diagram.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• 한국항행학회논문지
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• 제17권6호
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• pp.693-699
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• 2013

본 논문에서는 ITU-R M.1842-1 표준 권고안 Annex1에 따르는 ${\pi}/4$-DQPSK 모뎀에 대해 분석하고 시뮬레이션을 수행하였다. 우선 VHF 대역의 해상 이동통신에 대한 표준 및 기술동향을 소개하였다. Annex1에 제시된 ${\pi}/4$-DQPSK 모뎀은 25KHz의 대역폭에서 28.8Kbps 비트전송률을 제공하도록 제시되어 있다. 송수신기에서 RRC필터를 채용하는 ${\pi}/4$-DQPSK 모뎀의 시뮬레이션 프로세스에 대해 설명하고, 다양한 시뮬레이션 결과(시간영영 신호파형, 성좌도, 롤오프 팩터에 따른 전력스펙트럼밀도, Eye 다이어그램)들과 모뎀의 BER 성능을 제시하였다. 시뮬레이션 결과로부터, RRC 필터의 롤오프 팩터에 의해서 SNR에 따른 BER 성능에 미치는 영향이 다름을 확인하였고, 설계한 시뮬레이션 모델이 ITU-R M.1842-1 권고안에 제시된 스펙트럼 마스크 요구사항을 만족함을 알 수 있었다.

• ETRI Journal
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• 제26권6호
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• pp.589-596
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• 2004

Packaging technologies for a broadband and narrowband modulator with a traveling wave electro-absorption modulator (TWEAM) device were developed. In developing a broadband modulator, the effects of the device and packaging designs on the broadband performance were investigated. The optimized designs were obtained through a simulation with the result that we developed a broadband modulator with a 3 dB bandwidth of 38 GHz in the electrical-to-optical (E/O) response, an electrical return loss of less than -10 dB at up to 26 GHz, an rms jitter of 1.832 ps, and an extinction ratio of 5.38 dB in a 40 Gbps non-return to zero (NRZ) eye diagram. For analog application, the effect of the RF termination scheme on the fractional bandwidth was studied. The microstrip line with a double stub as a matching circuit and a laser trimming process were used to obtain an $S_{11}$ of -34.58 dB at 40 GHz and 2.9 GHz bandwidth of less than -15 dB.

• 조명전기설비학회논문지
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• 제20권9호
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• pp.11-17
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• 2006

We have theoretically investigated the effects of the interplay between the driving voltage of Mach-Zehnder(MZ) modulators and the bandwidth of low-pass filters(LPF) in 10[Gb/s] duobinary modulation systems. For the change of driving voltage ratios(driving voltage/switching voltage), the transmission performance has been evaluated over 200[km] of single-mode fiber(SMF) systems. For driving voltage ratios with smaller than 100[%], the transmission performance has been maintained and greatly affected by the bandwidth of LPFs than the driving voltage. For driving voltage ratios with larger than 100[%], the transmission performance has been degraded and is not sensitive to the bandwidth of LPFs. To see the limitation of driving voltage, we have reduced the driving voltage ratio to 50[%]. Our results suggest that 10[Gb/s] duobinary signals with driving voltage ratio with smaller than 100[%] have been transmitted over 200[km] SMF within 2[dB] power penalty without dispersion compensation. For the driving voltage ratio with 50[%], we have verified that the transmission performance was maintained.

• Progress in Superconductivity
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• 제6권1호
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• pp.7-12
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• 2004

Due to the very fast switching speed of Josephson junctions, superconductive digital circuit has been a very good candidate fur future electronic devices. High-speed and Low-power microprocessor can be developed with Josephson junctions. As a part of an effort to develop superconductive microprocessor, we have designed an RSFQ 4-bit ALU (Arithmetic Logic Unit) in a pipelined structure. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The RSFQ 1-bit block of ALU used in this work consisted of three DC current driven SFQ switches and a half-adder. We successfully tested the half adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached switches at the input ports to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this setup, 1-bit block of ALU was successfully tested up to 40 GHz. An RSFQ 4-bit ALU was fabricated and tested. The circuit worked at 5 GHz. The circuit size of the 4-bit ALU was 3 mm ${\times}$ 1.5 mm, fitting in a 5 mm ${\times}$ 5 mm chip.

• 한국광학회지
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• 제10권5호
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• pp.405-412
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• 1999

SSF 알고리즘의 고정된 구간을 개선하여 자동으로 구간을 선택함으로 계산시간을 줄인 Auto Z-step과, SSF 알고리즘에 사용되는 FFT 방법의 표본값을 자동적으로 줄여서 계산시간을 감소시킨 Auto T-step 알고리즘을 제안하였다. 2.5Gbps 100km 전송시 이 두 알고리즘을 사용한 것은 기존의 1km fixed step 알고리즘보다 1/120의 계산시간이 줄었고, 10Gbps 40km 전송시 최대 1/56으로 줄었으며, 오차는 모두-30㏈ 이하였다. eye diagram으로 kkm fixed step 알고리즘과 비교할 때 오차가 무시될 수 있음을 알 수 있었다.

• 마이크로전자및패키징학회지
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• 제23권4호
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• pp.69-77
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• 2016

We propose nano-scale Cu direct bonding technology using ultra-high density Cu nano-pillar (CNP) with for high stacking yield exascale 2.5D/3D integration. We clarified the joining mechanism of nano-scale Cu direct bonding using CNP. Nano-scale Cu pillar easily bond with Cu electrode by re-crystallization of CNP due to the solid phase diffusion and by morphology change of CNP to minimize interfacial energy at relatively lower temperature and pressure compared to conventional micro-scale Cu direct bonding. We confirmed for the first time that 4.3 million electrodes per die are successfully connected in series with the joining yield of 100%. The joining resistance of CNP bundle with $80{\mu}m$ height is around 30 m for each pair of $10{\mu}m$ dia. electrode. Capacitance value of CNP bundle with $3{\mu}m$ length and $80{\mu}m$ height is around 0.6fF. Eye-diagram pattern shows no degradation even at 10Gbps data rate after the lamination of anisotropic conductive film.

• Progress in Superconductivity
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• 제6권2호
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• pp.104-107
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• 2005

We have developed and tested an RSFQ 4-bit Arithmetic Logic Unit (ALU) based on half adder cells and de switches. ALU is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. We have simulated the circuit by using Josephson circuit simulation tools in order to reduce the timing problem, and confirmed the correct operation of the designed ALU. We used simulation tools of $XIC^{TM},\;WRspice^{TM}$, and Julia. The fabricated 4-bit ALU circuit had a size of $\3000{\ cal}um{\times}1500{\cal}$, and the chip size was $5{\cal} mm{\times}5{\cal}mm$. The test speeds were 1000 kHz and 5 GHz. For high-speed test, we used an eye-diagram technique. Our 4-bit ALU operated correctly up to 5 GHz clock frequency. The chip was tested at the liquid-helium temperature.

• Progress in Superconductivity
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• 제7권2호
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.