• 조명전기설비학회논문지
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• 제29권3호
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• pp.81-87
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• 2015

In order to effectively protect electrical and electronic circuits which are extremely susceptible to lightning surges, multi-stage surge protection circuits are required. This paper presents the operational characteristics of the two-stage hybrid surge protection circuit in extra-low voltage DC power lines. The hybrid surge protective device consists of the gas discharge tube, transient voltage suppressor, and series inductor. The response characteristics of the proposed hybrid surge protective device to combination waves were investigated. As a result, the proposed two-stage surge protective device to combination wave provides the tight clamping level of less than 50V. The firing of the gas discharge tube to lightning surges depends on the de-coupling inductance and the rate-of-change of the current flowing through the transient voltage suppressor. The coordination between the upstream and downstream components of the hybrid surge protective device was satisfactorily achieved. The inductance of a de-coupler in surge protective circuits for low-voltage DC power lines, relative to a resistance, is sufficiently effective. The voltage drop and power loss due to the proposed surge protective device are ignored during normal operation of the systems.

• ETRI Journal
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• 제30권3호
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• pp.412-420
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• 2008

A new scan partition architecture to reduce both the average and peak power dissipation during scan testing is proposed for low-power embedded systems. In scan-based testing, due to the extremely high switching activity during the scan shift operation, the power consumption increases considerably. In addition, the reduced correlation between consecutive test patterns may increase the power consumed during the capture cycle. In the proposed architecture, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the spectrum of unspecified bits in the test cubes. To optimize the proposed process, a novel graph-based heuristic to partition the scan chain into several segments and a technique to increase the number of don't cares in the given test set have been developed. Experimental results on large ISCAS89 benchmark circuits show that the proposed technique, compared to the traditional full scan scheme, can reduce both the average switching activities and the average peak switching activities by 92.37% and 41.21%, respectively.

• 조명전기설비학회논문지
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• 제26권12호
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• pp.1-8
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• 2012

The performance and lighting characteristics of the LED depend on cooling condition because the power LED generates lots of heat. In this paper, the effect of the generated heat from power LED module on lighting characteristics and performance is measured and evaluated. For experiments, the transient temperature of a power LED module with cooling condition is measured. In addition, the temperature and lighting characteristics of the LED module are measured during the steady state. As a result, the cooling condition is less effective on the lighting characteristics of the LED module at rated current but the cooling condition extremely affects those of the LED module over the rated current. Because high temperature of the power LED module causes the low phosphor conversion, luminance efficiency becomes low and color temperature becomes high. When power LED module are driven over the rated condition, higher temperature is directly related to lighting characteristics and performance of the LED module rather than higher current.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 B
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• pp.1159-1160
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• 2006

As the grid-connected photovoltaic power conditioning systems (PVPCS) are installed in many residential areas, this has raised potential problems of network protection on electrical power system. One of the numerous problems is an Island phenomenon. There has been an argument that because the probability of islanding is extremely low it may be a non-issue in practice. However, there are three counter-arguments: First, the low probability of islanding is based on the assumption of 100% power matching between the PVPCS and the islanded local loads. In fact, an island can be easily formed even without 100% power matching (the power mismatch could be up to 30% if only traditional protections are used, e.g. under/over voltage/frequency). The 30% power-mismatch condition will drastically increase the islanding probability. Second, even with a larger power mismatch, the time for voltage or frequency to deviate sufficient to cause a trip, plus the time required to execute the trip (particularly if conventional switchgear is required to operate), can easily be greater than the typical re-close time on the distribution circuit. And, third, the low-probability argument is based on the study of PVPCS. Especially, if the output power of PVPCS equals to power consumption of local loads, it is very difficult for the PVPCS to sustain the voltage and frequency in an island. Unintentional islanding of PVPCS may result in power-quality issues, interference to grid-protection devices, equipment damage, and even personnel safety hazards. So the verification of anti-islanding performance is strongly needed. In this paper, the authors propose the improved RPV method through considering power quality and anti-islanding capacity of grid-connected three-phase PVPCS in IEEE Std 1547 ("Standard for Interconnecting Distributed Resources to Electric Power Systems"). And the simulation and experimental results are verified.

• Journal of electromagnetic engineering and science
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• 제5권1호
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• pp.8-13
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• 2005

The InGaP/GaAs hetero-junction bipolar transistor(HBT) monolithic voltage-controlled dielectric resonator oscillator(VCDRO) is first demonstrated for a Ku-band low noise block down-converter(LNB) system. The on-chip voltage control oscillator core employing base-collector(B-C) junction diodes is proposed for simpler frequency tuning and easy fabrication instead of the general off-chip varactor diodes. The fabricated VCDRO achieves a high output power of 6.45 to 5.31 dBm and a wide frequency tuning range of ]65 MHz( 1.53 $\%$) with a low phase noise of below -95dBc/Hz at 100 kHz offset and -115 dBc/Hz at ] MHz offset. A]so, the InGaP/GaAs HBT monolithic DRO with the same topology as the proposed VCDRO is fabricated to verify that the intrinsic low l/f noise of the HBT and the high Q of the DR contribute to the low phase noise performance. The fabricated DRO exhibits an output power of 1.33 dBm, and an extremely low phase noise of -109 dBc/Hz at 100 kHz and -131 dBc/Hz at ] MHz offset from the 10.75 GHz oscillation frequency.

• 한국전자파학회논문지
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• 제18권5호
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• pp.553-562
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• 2007

본 논문에서는 극저주파 자계 세기를 원격으로 측정하기 위한 장치를 설계하고 제작하였다. 자계 측정기는 자계를 등방적으로 측정하기 위하여 3축 자계 센서를 사용하였으며, 측정 대역내 주파수에서 주파수 특성을 보상하기 위하여 등화기를 사용하였다. 3축 자계 센서의 출력 신호를 시간적으로 다중화 시켜, 3축간 균일한 이득 및 주파수 특성을 얻었다. 자계 측정 레벨 범위는 $0.01{\sim}10.0\;uT$이며, 측정 주파수 대역은 $40{\sim}180\;Hz$이 되도록 설계하였다. 제어 시스템은 무선으로 자계 측정기에 접근하며, 최대 접근 거리는 1.0 km이다. 제작된 장치의 측정 레벨 오차는 5% 이내이다. 제작된 장치는 고전압 송전선이 지나는 골프 연습장에 설치되었다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.506-517
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• 2015

This paper presents a 1.248 Gb/s - 2.918 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is $0.01{\mu}s$ the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a $0.11{\mu}m$ CMOS process, and the die area is $600{\mu}m{\times}250{\mu}m$. The power consumption of the receiver is 16 mW from the supply voltage of 1.1 V. The measured lock time of the CDR is less than 20 ns. The measured rms and peak jitter are $35.24ps_{p-p}$ and $4.25ps_{rms}$ respectively for HS-G2 mode.

• 한국정보통신학회논문지
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• 제10권8호
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• pp.1465-1470
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• 2006

본 논문에서는 단거리 무선 통신의 새로운 국제 표준으로 부상하고 있는 2.4 GHz ZigBee 응용을 위한 저전력 CMOS LNA(Low Noise Amplifier)를 설계하였다. 제안한 구조는 전류 재사용 기법을 이용한 2단 cascade구조이며 회로의 설계에서 TSMC $0.18{\mu}m$ CMOS 공정을 사용하였다. 전류 재사용단은 두 단의 증폭기 전류를 공유함으로써 LNA의 전력 소모를 적게 하는 효과를 얻을 수 있다. 본 논문에서는 LNA설계 과정을 소개하고 ADS(Advanced Design System)를 이용한 모의실험 결과를 제시하여 검증하였다. 모의실험 결과, 1.0V의 전압이 인가될 때 1.38mW의 매우 낮은 전력 소모를 확인하였으며 이는 지금까지 발표된 LNA 중 가장 낮은 값이다. 또한 13.83dB의 최대 이득, -20.37dB의 입력 반사 손실, -22.48dB의 출력 반사 손실 그리 고 1.13dB의 최소 잡음 지수를 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 학술대회지
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• pp.494-498
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• 2004

In this paper, the design of a CMOS exponential V-I converter (EVIC,) based on Taylor's concept, is presented. The composite NMOS transistor is used for realizing the exponential characteristics. In a 0.25 $\mu$m CMOS process, the simulations show more than 20 dB output current range and 15 dB linear range with the linearity error less than $\pm$ 0.5 dB. The power dissipation is less than 0.3 mW with $\pm$ 1.5 V supply voltage. The proposed EVIC can be used for the design of an extremely low­voltage and low-power variable gain amplifier (VGA) and automatic gain control (AGC).

• 한국전자통신학회논문지
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• 제13권5호
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• pp.1093-1100
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• 2018

웨어러블 기기에서 반도체의 소형화 및 저전력 기술이 빠르게 진행됨에 따라 다양한 초소형 형태의 응용서비스를 제공할 수 있게 되었다. 최근에는 태양열, 피에조, 마찰 등 다양한 에너지 하베스터를 이용해 저전력 반도체는 매우 낮은 전원으로도 동작할 수 있게 되었다. 웨어러블 상황에서의 대부분에 에너지 하베스팅은 비연속적(non-linear)으로 발전된다. 이에 따라 본 연구에서는, 3Hz의 낮은 주파수기반 디바이스 플랫폼을 제작하여 실험적으로 평가하였다. 본 연구는 비연속적 발전 환경을 고려해, 2단계의 저장환경과 사용된 에너지 발전소자의 맞춘 에너지 고효율 변환 플랫폼 설계하였다. 또한, 비연속적 에너지 수집 환경에서 안정적인 에너지를 저장 유지를 통해 약 4.67mW/min 발전하였다.