• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.15 no.4
• /
• pp.344-348
• /
• 2002

As microelectronics technology continues to progress, there is also a continuous demand on highly integration and miniaturization of systems. For example, it is desirable to package several integrated circuits together in multilayer structure, such as multichip modules, to achieve higher levels of compactness and higher performance. Passive components (i.e., capacitors, resistors, and inductors) are very important fort many MCM applications. In addition, the low-temperature co-fired ceramic (LTCC) process has considerable potential for embedding passive components in a small area at a low cost. In this paper, we investigate a method of statistically modeling integrated passive devices from just a small number of test structures. A set of LTCC inductors is fabricated and their scattering parameters (s-parameters) are measured for a range of frequencies from 50MHz to 5GHz. An accurate model for each test structure is obtained by using a building block based modeling methodology and circuit parameter optimization using the HSPICE circuit simulator.

• Journal of the Korea Safety Management & Science
• /
• v.19 no.4
• /
• pp.309-316
• /
• 2017

Recently, the outboard engine system of internal combustion engine is widely used in the field of small ship propulsion. However, the internal combustion engine has serious problems of energy depletion and environmental problems, so electric propulsion methods are being studied. In this paper, we have developed important motors and controllers of electric propulsion system for small marine outboard motors. The motor design was performed through the motor characteristics analysis method, and the 30Kw system was developed through the BEMF processing circuit and the power conversion circuit by the embedded microprocessor. This study was carried out through government supported projects and achieved quantitative targets through accredited institutions.

• Journal of the Optical Society of Korea
• /
• v.15 no.1
• /
• pp.9-14
• /
• 2011

In this study, the internal structure of an optical waveguide embedded in a flexible optical circuit board is observed with a confocal microscope. In order to increase the light reflection from an internal material interface with a very small index difference, and thus enhance the signal contrast, a theta microscopy scheme has been integrated into a conventional confocal microscope, and a high NA oil-immersion lens has been used. The interface reflectivity is increased from roughly 0.0015% to 0.025% by the proposed method, and the internal structure can thus be successfully measured.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.12 no.3
• /
• pp.312-320
• /
• 2019

In this paper, we design a 512Kb eFlash IP using 110nm eFlash cells. We proposed eFlash core circuit such as row driver circuit (CG/SL driver circuit), write BL driver circuit (write BL switch circuit and PBL switch select circuit), read BL switch circuit, and read BL S/A circuit which satisfy eFlash cell program, erase and read operation. In addition, instead of using a cross-coupled NMOS transistor as a conventional unit charge pump circuit, we propose a circuit boosting the gate of the 12V NMOS precharging transistor whose body is GND, so that the precharging node of the VPP unit charge pump is normally precharged to the voltage of VIN and thus the pumping current is increased in the VPP (boosted voltage) voltage generator circuit supplying the VPP voltage of 9.5V in the program mode and that of 11.5V in the erase mode. A 12V native NMOS pumping capacitor with a bigger pumping current and a smaller layout area than a PMOS pumping capacitor was used as the pumping capacitor. On the other hand, the layout area of the 512Kb eFlash memory IP designed based on the 110nm eFlash process is $933.22{\mu}m{\times}925{\mu}m(=0.8632mm^2)$.

• Journal of information and communication convergence engineering
• /
• v.8 no.2
• /
• pp.197-200
• /
• 2010

The FLL(frequency locked loop) circuit is used to generate an output signal that tracks an input reference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL is designed to allow the circuit to be fully integrated. In this paper, the temperature stable FLL circuit is designed by using full CMOS transistors. When the temperature is varied from $-20^{\circ}C$ to $70^{\circ}C$, the variation of output frequency is about from -2% to 1.6% from HSPICE simulation results.

• Proceedings of the Korean Institute of Building Construction Conference
• /
• 2019.05a
• /
• pp.262-263
• /
• 2019

In this study, a sensor for detecting corrosion of rebar embedded in reinforced concrete structures was fabricated and its performance was verified. In order to monitor the open circuit potential(OCP) of the rebar embedded in reinforced concrete, a concrete embedded solid electrode was constructed as a sensor using MnO2. The OCP of the rebar could be observed using a sensor and a data logger. The decrease of the OCP to -510mV (vs.MnO2) or less was judged to be corrosion of the rebar. Since it is a solid-mediated sensor, it is more stable and durable than an electrode using an aqueous solution, and it is considered that the corrosion state of the rebar can be monitored for a long period of time.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.24 no.7
• /
• pp.885-890
• /
• 2020

In the distance measurement system the time-to-digital conversion circuit used measures the distance using the time interval between the start signal and the stop signal. The time interval is generally converted to digital information using a counter circuit considering the response speed. Therefore, a clock signal with a high frequency is required to improve precision, and a clock signal with a high frequency is also required to measure fine distances. In this paper, a counter circuit was designed to increase the accuracy of distance measurement while using the same frequency. The circuit design was performed using a 0.18㎛ CMOS process technology, and the operation of the designed circuit was confirmed through HSPICE simulation. As a result of the simulation, it is possible to obtain an improvement of four times the precision compared to the case of using a general counter circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.12
• /
• pp.54-60
• /
• 2007

This paper proposes a built-in-self-repair (BISR) structure using 2-dimensional spare memory to effectively self-repair faults of an embedded memory. In case of multiple faults in the same row (column) of an embedded memory, the previous method using 1-D spare column (row) memory needs the same number of spare memory columns (rows) as the number of faults to self-repair them. while the new method using 2-D spare memory needs only one spare row (column) to self-repair them. Also, the virtual divided memory is adopted to be able to self-repair using not a full spare column memory but the only partial spare column memory corresponding to the faults. A self-repair circuit with $64\times1-bit$ core memory and $2\times8$ 2-D spare memory is designed. And the circuit includes a built-in-self-test block using the 13N March algorithm. The circuit has been implemented using the $0.25{\mu}m$ MagnaChip CMOS process and has $1.1\times0.7mm^2$ chip area with 10,658 transistors.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1117-1120
• /
• 1998

BIST architecture and circuit design are presented for the self-test of various datapath megacells including embedded SRAM, barrel shifter, adder and multiplier. The BIST architecture is composed of VCO, ROM, comparator and otehr control logic to measure the megacell' performance up to 300MHz. PC interface and control logic are also implemented to perform the manual testing of each megacell with various test patterns. The control logic was designed using VHDL and its circuit is synthesized using Synopsys for $0.6\mu$ 1-poly, 3-matal CMOS technology.

• Journal of information and communication convergence engineering
• /
• v.8 no.5
• /
• pp.566-569
• /
• 2010

This paper describes the sinusoidal, pulse, triangular oscillator using second generation current conveyor. To obtain the sinusoidal waveform the circuit blocks are constructed by using all pass filter and integrator. The pulse and the triangular waveforms are obtained from the output of sinusoidal oscillator. The peak-to-peak voltages of sinusoidal and triangular waveforms can be easily controlled by the dc offset voltage. Also the output frequency of the oscillator can be controlled by varying passive elements. The designed circuit is verified by HSPICE simulation.