• Corrosion Science and Technology
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• v.3 no.3
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• pp.118-126
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• 2004

The correlation between sensor output and corrosion rate of reinforcing steel was evaluated by laboratory electrochemical tests in saturated $Ca(OH)_2$ with 3.5 wt.% NaCl and confirmed in concrete environment. In this paper, two types of electrochemical probes were developed: galvanic cells containing of steel/copper and steel/stainless steel couples. Potentiodynamic test, weight loss measurement, monitoring of open-circuit potential, linear polarization resistance (LPR) measurement and electrochemical impedance spectroscopy (EIS) were used to evaluate the corrosion behavior of steel bar embedded in concrete. Also, galvanic current measurements were conducted to obtain the charge of sensor embedded in concrete. In this study, steel/copper and steel/stainless steel sensors showed a good correlation in simulated concrete solution between sensor output and corrosion rate of steel bar. However, there was no linear relationship between steel/stainless steel sensor output and corrosion rate of steel bar in concrete environment due to the low galvanic current output. Thus, steel/copper sensor is a reliable corrosion monitoring sensor system which can detect corrosion rate of reinforcing steel in concrete structures.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2001.04a
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• pp.1117-1120
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• 2001

Chemical mechanical planarization(CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There have been serious problems in CMP in terms of repeatability and defects in patterned wafers. Since IBM's official announcement on Copper Dual Damascene(Cu2D) technology, the semiconductor world has been engaged in a Cu2D race. Today, even after~3years of extensive R&D work, the End-of-Line(EOL) yields are still too low to allow the transition of technology to manufacturing. One of the reasons behind this is the myriad of defects associated with Cu technology. Especially, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasive and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using Ce$O_2$ is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method for developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• Design & Manufacturing
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• v.14 no.1
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• pp.15-21
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• 2020

Smart systems in different application areas such as automotive, medical and consumer electronics require a novel manufacturing method of electronic, optical and mechanical functions into products. Traditional methods including mechanical assembly, bonding of plastic and electronic circuit cause the problems in large size of products and complicated manufacturing processes. In this study, thermoforming and film insert molding were applied to fabricate a dome shaped plastic part embedded with electronic circuits. The deformation of patterns printed on PET film was predicted by thermoforming simulation using T-SIM, and the results were compared with those by experiment. In order to decrease spring-back after thermoforming, the Taguchi method of design of experiment was used. Through ANOVA analysis, it was found that mold temperature was the most dominant parameter for spring-back. By using flow analysis, gate design was performed to decrease injection pressure. During film insert molding, the wash-out of ink printed on film occurred for Polycarbonate. When the resin was changed to PMMA, the wash-out disappeared due to low melt temperature.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.746-753
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• 2001

GenBIST implemented in this paper is an automatic CAD tool, which can automatically generate circuitry in VerilogHDL code based on user defined information for the memory testing. While most commercial and conventional CAD tools adopt a method in which they make memory-testing algorithms as a library to generate circuitry, our tool can generate circuitry according to the user-defined algorithm, which makes application of various algorithms easier. In addition, memory BIST circuitry can be shared with other memories by supporting embedded memories in our tool. Also, extra pins for the memory testing are not requited when boundary scan technique is combined.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.1
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• pp.99-107
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• 2001

In this paper, we implemented memory BIST circuit based on ION march algorithm, and the IEEE 1149.1 has been designed as main controlJer for embedded memory testing. The implemented memory BIST can be used for word-oriented memory since it adopts background data, this is avaliable for word-oriented memory. It is able to detect all stuck-at faults, transition faults, coupling faults, and address decoder faults in the word-oriented memory. Memory BIST and IEEE 1149.1 are described at RTL level in Verilog-HDL, and synthesized with the Synopsys. The synthesized circuits are fully velified using VerilogXL and memory cell generated by memory compiler.

• Journal of the Korean Society for Precision Engineering
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• v.18 no.12
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• pp.192-199
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• 2001

Chemical mechanical planarization (CMP) has emerged as the planarization technique of choice in both front-end and back-end integrated circuit manufacturing. Conventional CMP process utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. There hale been serious problems in CMP in terms of repeatability and deflects in patterned wafers. Especial1y, dishing and erosion defects increase the resistance because they decrease the interconnection section area, and ultimately reduce the lifetime of the semiconductor. Methods to reduce dishing & erosion have recently been interface hardness of the pad, optimization of the pattern structure as dummy patterns. Dishing & erosion are initially generated an uneven pressure distribution in the materials. These defects are accelerated by free abrasives and chemical etching. Therefore, it is known that dishing & erosion can be reduced by minimizing the abrasive concentration. Minimizing the abrasive concentration by using CeO$_2$is the best solution for reducing dishing & erosion and for removal rate. This paper introduce dishing & erosion generating mechanism and a method fur developing a semi-rigid abrasive pad to minimize dishing & erosion during CMP.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.131-143
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• 1996

In this paper, we propose the improved structure of fully interconnected ATM Switch to develop the small sized switch element and represent practical implementation of switch network. As the part II of the full study about structure and implementation of fully interconnected ATM Switch, this paper especially describes the implementation of an ATM switching element with 8 input port and 8 output port at 155 Mbits/sec each. The single board switching element is used as a basic switching block in a small sized ATm switch for ATM LAN Hub and customer access node. This switch has dedicated bus in 12 bit width(8 bit data + 4 bit control signal) at each input and output port, bit addressing and cell filtering scheme. In this paper, we propose a practical switch architecture with fully interconnected buses to implement a small-sized switch and to provide multicast function withoutany difficulty. The design of switching element has become feasible using advanced CMOS technology and Embedded Gate Array technology. And, we also represent Application Specific Integrated Circuit(ASIC) of Switch Output Multiplexing Unit(SOMU) and 12 layered Printed Circuit Board for interconnection network of switch.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.3
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• pp.95-100
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• 2004

This paper reports a potential problem in the electrical performance of the silicide film to silicon contacts with respect to the scaling trend in integrated circuit (IC) devices. The effects of elastic strain on the agglomeration of the coherent silicide film embedded in an infinite matrix are studied employing continuum linear elasticity and finite-difference numerical method. The interface atomic diffusion is taken to be the dominant transport mechanism where both capillarity and elastic strain are considered for the driving forces. Under plane strain condition with elastically homogeneous and anisotropic system with cubic symmetry, the dilatational misfit and the tetragonal misfit in the direction parallel to the film thickness are considered. The numerical results on the shape evolution agree with the known trend that the equilibrium aspect ratio of the film increases with the elastic strain intensity. When the elastic strain intensity is taken to be only a function of the film size, the flat film morphology with a large aspect ratio becomes increasingly unstable since the equilibrium aspect ratio decreases, as the film scales. The shape evolution results in a large decrease in contact to silicon area, and may deteriorate the electrical performances.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.8
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• pp.853-859
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• 2014

This study presents a technique for extracting all the extrinsic parameters of HEMTs by minimizing the residual errors between a pinch-off cold-FET's gate and drain pad de-embedded Z-parameters and its modeled Z-parameters calculated by the cold-FET's remaining parameters. The presented technique allows us to successfully extract the remaining extrinsic parameter values as well as the gate and drain pad capacitance value without the additional fabrications of the gate and drain dummy pad.

• Laser Solutions
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• v.17 no.3
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• pp.19-23
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• 2014

To directly engrave circuit-line patterns as wide as $6{\mu}m$ in a buildup film to be used as an IC substrate, we applied a projection ablation technique in which an 8 inch dielectric ($ZrO_2/SiO_2$) mask, a DPSS 355nm laser instead of an excimer laser, a ${\pi}$-shaper and a galvo scanner are used. With the ${\pi}$-shaper and a square aperture, the Gaussian beam from the laser is shaped into a square flap-top beam. The galvo scanner before the $f-{\theta}$ lens moves the flat-top beam ($115{\mu}m{\times}105{\mu}m$) across the 8 inch dielectric mask whose patterned area is $120mm{\times}120mm$. Based on the results of the previous research by the authors, the projection ratio was set at 3:1. Experiments showed that the average width and depth of the engraved patterns are $5.41{\mu}m$ and $7.30{\mu}m$, respectively.